Peking University

Boe Technology Group Co., Ltd.

Lianmao Peng

Zhiyong Zhang

Xuelei Liang

Sheng Wang

Fangzhen Zhang

Guanbao Hui

Qing Chen

Jiye Xia

Boyuan Tian

Qiuping Yan

Chenyi Zhao

Donglai Zhong

Haiyan Zhao

Jia Si

A dual-gate transistor and its production method are disclosed. An auxiliary gate is connected to the power supply of the integrated circuits, to form thick and high square-shaped potential barrier of minority carriers adjacent to the drain electrode, while the potential barrier is transparent for the majority carriers from the source electrodes. The potential barrier can effectively inhibit reverse minority carrier tunneling from the drain electrode at large drain-source voltage. The transistor can be easily turned on at small drain-source voltage, without significantly decreasing the on-state current. The dual-gate transistor can significantly suppress ambipolar behavior with increased current on/off ratio and reduced power consumption, and maintain the high performance. Based on transistors, strengthened CMOS circuits can have high noise margin, low voltage loss, reduced logic errors, high performance and low power consumption. Moreover, no additional power sources are added to the circuit, which makes it suitable for ultra-large-scale integrated circuits.

Dual-gate transistors and their integrated circuits and preparation method thereof

The present disclosure provides a thin-film transistor having a plurality of carbon nanotubes in its active layer, its manufacturing method, and an array substrate. The manufacturing method as such comprises: forming an insulating layer to at least substantially cover a channel region of the active layer between a source electrode and a drain electrode of the thin-film transistor, wherein the insulating layer is configured to substantially insulate from an environment, and have substantially little influence on, the plurality of carbon nanotubes in the active layer.

Thin-film transistor including carbon nanotubes, manufacturing method, and array substrate

The present disclosure provides a carbon nanotube thin film transistor (CNT-TFT) and its manufacturing method. The carbon nanotube thin film transistor includes a source electrode, a drain electrode, a channel region, a plurality of protrusions, and a carbon nanotube layer. The channel region is between the source electrode and the drain electrode. The plurality of protrusions are at, and extend in a length direction of, the channel region. The carbon nanotube layer is disposed over the plurality of protrusions, and comprises a plurality of carbon nanotubes.

Carbon nanotube thin film transistor and manufacturing method thereof

The present application relates to a method of increasing density of aligned carbon nanotubes. Firstly, aligned carbon nanotubes grown on a substrate is transferred to a stretched retractable film. The retractable film is then shrunk along a direction which is perpendicular to the alignment direction of the carbon nanotubes to obtain high density carbon nanotubes. The array of aligned carbon nanotubes is finally transferred from the retractable film to a target substrate. The disclosed method can efficiently obtain high-density high-quality aligned carbon nanotubes at low cost.

Method for increasing density of aligned carbon nanotubes

A carbon nano-tube based photoelectric device includes a substrate and a carbon nanotube (CNT) over the substrate. The CNT comprises a first end and a second end, wherein the CNT has a CNT work function. A high work-function electrode over the substrate is in electric contact with the first end of the CNT. The high work-function electrode has a first work function higher than the CNT work function. A low work-function electrode over the substrate is in electric contact with the second end of the CNT. The low work-function electrode has a second work function lower than the CNT work function. The CNT can form a conductive channel between the high work-function electrode and the low work-function electrode. The carbon nano-tube based photoelectric device also includes a dielectric material is in contact with a side surface of the CNT and a conductive material in contact with the dielectric material.

Carbon-nanotube based opto-electric device

Our invention discloses a self-aligned-gate structure for nano FET and its fabrication method. One dimension semiconductor material is used as conductive channel, whose two terminals are source and drain electrodes. Gate dielectric grown by ALD covers the area between source electrode and drain electrode, opposite sidewalls of source electrode and drain electrode, and part of upper source electrode and drain electrode. Gate electrode is deposited on gate dielectric by evaporation or sputtering. Total thickness of gate dielectric and electrode must less than source electrode or drain electrode. Gate electrode between source electrode and drain electrode is electrically separated from source and drain electrode by gate dielectric. The fabrication process of this self-aligned structure is simple, stable, and has high degree of freedom. Nearly the whole conductive channel between source electrode and drain electrode is covered by gate electrode, so the control efficiency of the gate over the conductive channel, described as transconductance, can be greatly enhanced. Additionally, there is no restriction on material of gate dielectric or electrode, so the devices' threshold voltage can be adjusted to satisfy the requirements of large scale integrated circuit.

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Beijing, China

Lianmao Peng