Qualcomm Incorporated

Liangxiao Hu

Andrew Evan Gruber

Yun Du

Chun Yu

Gang Zhong

Chihong Zhang

Eric Demers

Zilin Ying

Baoguang Yang

Fei Wei

Minjie Huang

Yang Xia

Jing Han

Jian Jiang

A graphics processing unit (GPU) utilizes block general purpose registers (bGPRs) to load multiple waves of samples for an instruction group into a processing pipeline and receive processed samples from the pipeline. The GPU acquires a credit for the bGPR for execution of the instruction group for a first wave using a persistent GPR and the bGPR. The GPU refunds the credit upon loading the first wave into the pipeline. The GPU executes a subsequent wave for the instruction group to load samples to the pipeline when at least one credit is available and the pipeline is processing the first wave. The GPU stores an indication of each wave that has been loaded into the pipeline in a queue. The GPU returns samples for a next wave in the queue from the pipeline to the bGPR for further processing when the physical slot of the bGPR is available.

Deferred GPR allocation for texture/load instruction block

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Liangxiao Hu