Alpha & Omega Semiconductor Corporation

Siemens Healthcare Gmbh

Advanced Micro Devices Corporation

Freescale Semiconductor,inc.

Mettler-toledo International Trading (shanghai) Co., Ltd.

Mettler Toledo (changzhou) Measurement Technology Ltd.

Halo Microelectronics Co., Ltd.

Mettler-toledo (changzhou) Precision Instruments Ltd.

Shanghai Pharmaceuticals Holding Co., Ltd.

Liang Zhao

Yan Xun Xue

Jun Lu

Lei Shi

Yueh-Se Ho

Ping Huang

Hamza Yilmaz

Yuping Gong

Xiang Sean Zhou

Yiqiang Zhan

Rui Liu

Xiaotian Zhang

Ming-Chen Lu

Hai Tao

Ping Wu

Esther Raithel

Guangxin Xia

Zhigang Peng

Yanjun Liu

Shuang Han

Shu Liao

Jun Fan

Di Li

Ning Zhou

YuBin Yao

Zhi Qiang Niu

Lei Duan

Limin Wang

Yu Zhao

Wanchuan Hu

Jiansheng Han

Zhennan Yan

GuoFeng Lian

Kailai Wang

Le Shi

Feng Ye

Peng Jiang

Dongsong Li

Guangteng Zhu

Jian Gong

Xu Sun

Ao Chen

Yimo Gao

Detection system using x-rays

An apparatus includes a first group of switches connected in series, a second group of switches connected in series, a first flying capacitor between a first common node and a third common node of the first group of switches, a second flying capacitor between a first common node and a third common node of the second group of switches, wherein the first group of switches and the second group of switches are configured such that the apparatus operates in one of three operating modes including a bypass operating mode, a hybrid operating mode and a boost/buck operating mode.

Power conversion circuit, power conversion system and power chip

A salt of a quinazoline derivative (N-[4-(3-chlorine-4-fluoroanilino)]-7-(3-morpholinepropanol)-6-(2-fluoroacrylamide)-quinazoline, the structure thereof is as represented by formula I). Compared with a known quinazoline derivative, the salt of the quinazoline derivative has one or more improved properties and at least has better water solubility, wherein a citrate, a benzene sulfonate, and an ethanedisulphonate thereof further have better crystallinity and are not easy to absorb moisture. 

Salt of quinazoline derivative, preparation method therefor and application thereof

In a method for alpha angle measurements of a bone joint based on magnetic resonance imaging (MRI) data of the bone joint, a three-dimensional (3D) bone surface image of the bone joint is generated based on two-dimensional (2D) segmentations on radial plane slices of the bone joint. Based on the 3D bone surface image, a head center of a head of the bone joint and a neck axis of a neck of the bone joint are estimated. An alpha angle model is constructed based on the estimated head center and neck axis. Further, the alpha angle measurement is determined for each of the radial plane slices of the bone joint based on the constructed alpha angle model.

System and method for angle measurements using magnetic resonance images

A framework for cross-modality image synthesis. A first and second model may be trained using respective first and second pairs of complementary images and corresponding first and second ground truth images that represent first and second views of a region of interest. The first and second pairs of complementary images may be acquired by a first modality and the first and second ground truth images may be acquired by a second modality. A combinational network may further be trained to combine features from the first and second models. At least one synthetic second modality image may then be generated by passing current images through the trained first or second model and the combinational network, wherein the current images are acquired by the first modality and represent the first or second view of the region of interest.

Cross-modality image synthesis

In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator.

Refresh scheme in a memory controller

A method for automatically detecting a region of interest in a digital medical image, comprising over-segmenting the image into a plurality of superpixels through use of an over-segmentation algorithm; for each pair of neighboring superpixels in the plurality of superpixels, computing, through a machine learning algorithm, the probability of each pair being in one of three predetermined classes; for each superpixel in the plurality of superpixels, computing a probability of the superpixel being in the region of interest; generating an edge map from computing each pixel's value based on the computed superpixel probabilities; applying an extended Hough transform to the generated edge map to generate a Hough parameter counting space; determining the optimal quadrilateral in the Hough parameter counting space by excluding false positive edges; and designating the region of interest as being within the boundary of the determined optimal quadrilateral.

Automated region of interest detection using machine learning and extended Hough transform

A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Method for packaging a power device with bottom source electrode

A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

Packaging structure of a semiconductor device

A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.

Method for preparing semiconductor devices applied in flip chip technology

The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.

Stacked multi-chip bottom source semiconductor device and preparation method thereof

A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

Stacked power semiconductor device using dual lead frame

Semiconductor package and fabrication method thereof

A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

Manufacturing method of a semiconductor package of small footprint with a stack of lead frame die paddle sandwiched between high-side and low-side MOSFET

A solid-state memory device has a memory interface that includes a timing signal port for receiving a timing signal, a data transfer port, a data transfer module for transferring blocks of data signals between the data transfer port and the memory module, and a selectable delay module for providing a selected delay between transitions in the data signals DQ and transitions in the timing signals DQS. The memory interface also has a delay controller for setting the selected delay, for detecting a variation in a delay produced by the selectable delay module relative to a reference delay, for controlling a pause in transfer of a block of the data signals DQ, and for adjusting the selected delay during the pause.

Timing control in synchronous memory data transfer

Growing community of inventors

Shanghai, China

Liang Zhao