Freescale Semiconductor,inc.

Nxp Usa, Inc.

Siemens Aktiengesellschaft

Nanjing University

Siemens Ltd., China

Liang Zhang

Jianzhou Wu

Jie Jin

Hao Zhi

Zhengxiang Wang

Yizhong Zhang

Yang Wang

Yan Huang

Jiawei Fu

Zhihong Cheng

Wei Luo

Jia Chen

Wangsheng Mei

Jun Zhang

Wei Sun

Peidong Wang

Yikun Mo

Xiuqiang Xu

Yan Xiao

Jia Zhu

Li Hong Hu

Jianyu Yu

Stefan Höhe

Ping Ping Jin

The present invention discloses a method for preparing a sodium interface and a method for preparing a sodium-based optical structure device. This sodium interface is prepared in an inert gas atmosphere by the following steps: (1) melting solid sodium metal into liquid by heat, and stripping off solid oxides and impurities on the surface of the molten sodium metal to obtain pure liquid sodium with metallic luster; and (2) spin-coating a dielectric substrate with the liquid sodium to obtain the sodium interface tightly attached to the dielectric substrate. The prepared sodium interface can be used as a plasmon polariton material for use in plasmon polariton optical waveguides, nano-lasers and the like.

Method for preparing sodium interface and method for preparing sodium-based optical structure device

An address identification method, apparatus, system, storage medium, a processor and a terminal are disclosed. In an embodiment, the method includes: defining a screening library including at least one expected attribute value describing an expected state value of a device parameter to be addressed in an operating mode of an industrial device; acquiring a data group including an actual state value generated in the operating mode and an address where the actual state value is stored; for each address, extracting an actual attribute value, stored in the address, of the actual state value; comparing the actual attribute value with the expected attribute value, determining the actual state value corresponding to the actual attribute value which complies with the expected attribute value, and determining, from the data group, an address corresponding to the selected actual state value; and taking the selected address as a final address and outputting same.

Address identification method, apparatus and system, and storage medium, processor and terminal

A buffer stage for amplifying a clock signal generated by a current controlled oscillator that receives a first current at a first supply voltage from a first current source. The buffer stage comprises an input terminal configured to receive the clock signal; an output terminal configured to output a buffered signal; at least one buffer, coupled between the input and output terminal, configured to receive a second current at a second supply voltage and buffer the clock signal to generate the buffered signal; a clamping circuit that receives the first current and the second current, and generates a first supply voltage and a second supply voltage. The clamping circuit clamps the second supply voltage equal to the first supply voltage.

Buffer stage for use with a current controlled oscillator

A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.

Current-controlled oscillator with start-up circuit

Embodiments provide a node state detection method and device for detecting a running state of a target node in a non-network positioning system. The method includes: acquiring signal data, the signal data including data of at least one wireless signal received by a data acquisition terminal during one movement within the system. The data acquisition terminal is configured to pass through the target node during the movement. The method further includes determining whether the acquired signal data includes a feature indicated by standard signal feature information and determining the running state of the target node according to a determination result. The embodiments achieve automatic detection on a running state of a node in the non-network positioning system.

Node state detection method and device for non-network positioning system

A relaxation oscillator for generating a low temperature coefficient (LTC) clock signal includes a reference voltage generator and an oscillator. The reference voltage generator generates an LTC current and a bandgap reference voltage. The reference voltage generator includes positive temperature coefficient (PTC) resistors to compensate for the effects of temperature variations. The oscillator receives the LTC current and the bandgap reference voltage, and generates a clock signal. In another embodiment, the reference voltage generator generates a charge current that varies with temperature. The oscillator receives the charge current and generates first and second output signals. Set and reset comparators include PTC resistors that determine the gains of the set and reset comparators. The PTC resistors compensate for variation in the first and second output signals due to the temperature variations by varying the gains of the set and reset comparators.

Low temperature coefficient clock signal generator

A multi-bit flip-flop has first and second one-bit flip-flops. The multi-bit flip-flop employs inter-cell clock switch (CSW) sharing in which the first and second one-bit flip-flops share at least one clock switch. The multi-bit flip-flop may also employ intra-cell CSW sharing in which at least one of the first and second one-bit flip-flops shares at least one clock switch. The inter-cell CSW sharing enables implementation of multi-bit flip-flops with fewer clock switches and possibly fewer data devices, while reducing power consumption, including state retention power gating power reduction.

Multi-bit flip-flop with shared clock switch

A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.

Rail-to-rail comparator with shared active load

An electrical system can selectively power a load via a USB connection or via another power source, such as a wireless power transfer path. An integrated switch controller determines whether to power the load via the USB connection or the other power sources and controls two external transistors via a single I/O pin connection to implement that determination. The switch controller determines the greater of two voltages: a voltage associated with the USB connection and a voltage associated with the other power source. The switch controller also determines whether there is a valid USB connection. The switch controller circuitry that controls the two external transistors is powered at the greater voltage to ensure that the external transistors are appropriately and securely turned on or off.

Power switch control between USB and wireless power system

A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.

Rail-to-rail comparator with built-in constant hysteresis

A true random number generator (RNG) has one or more oscillators and an output register for storing a random number output. Each of the oscillators is activated, successively, in a free-running oscillation phase, and a capture phase during which the oscillator is quiescent. The output register latches during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase. The random number output is derived from the latched end states.

True random number generator with repeatedly activated oscillator

A voltage supply for providing a clamped voltage to a circuit element to be protected against electrical overstress (EOS) has a reference voltage module and a voltage clamp module. The reference voltage module has a first field-effect transistor (FET) whose source and drain are connected in series between a programmable reference current source and a first resistor across a power supply. The gate of the first FET is connected to its drain to provide a reference voltage defined by the reference current flowing in the first resistor. The voltage clamp module has a second FET whose gate receives the reference voltage and whose source is connected to provide to the protected circuit element the clamped voltage whose variation is limited by the reference voltage.

Voltage clamping circuit

A low voltage ripple charge pump with slew rate control includes a frequency divider, a clock generator, a current mirror, a switching circuit, a diode network, two capacitors, and a comparator. The frequency divider generates a clock signal from an oscillating signal. The clock generator generates first and second clock signals from the clock signal. The current mirror generates first and second current signals using a reference current. The switching circuit generates first and second voltage signals using the first and second clock signals and the first and second current signals. The comparator generates the oscillating signal based on the first and second voltage signals. The capacitors receive the voltage signals and are connected to the diode network for generating an output signal. The charge pump has low output voltage ripple with small filtering capacitance, which is achieved via slew rate control.

Low voltage ripple charge pump with shared capacitor oscillator

A band gap reference voltage generator has first and second current conduction paths between a first node and a second node. The first current conduction path has first resistive elements in series with a first forward-biased PN junction element. A tap is connected selectively to the first resistive elements through switches that are controllable to select a voltage divider ratio at the tap. The second current conduction path includes a second resistive element in series with a second PN junction element of greater current density than the first PN junction. A voltage error amplifier has inputs connected to the tap and the second PN junction element, and an output for providing a thermally compensated output voltage V. A feedback path applies the output voltage Vthrough a third resistive element to the first node.

Band gap reference voltage generator

A rail to rail differential buffer input stage includes n-type and p-type input differential transistor pairs connected in voltage follower configuration to the power supply rails. A reference voltage generator includes a reference differential transistor pair generating a dynamic reference voltage relative to the common mode input voltage. Dummy n-type and p-type transistor pairs have current conducting paths connected in parallel with the input differential pairs and are controlled by the dynamic reference voltage to divert supply rail current away from and deactivate one of the associated input differential pairs when the common mode input voltage is further from the dynamic reference voltage than a threshold value. Both the dummy pairs conduct and both the input differential pairs are activated when the common mode input voltage is closer to the dynamic reference voltage Vthan the threshold value so that the overall transconductance of the buffer input stage remains constant.

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Suzhou, China

Liang Zhang