Changxin Memory Technologies, Inc.

Huawei Technologies Co., Limited

Integrated Device Technology, Inc.

Guangdong Oppo Mobile Telecommunications Corp., Ltd.

Dow Global Technolgoies LLC

Micron Technology Incorporated

Hefei University of Technology

Hon Hai Precision Industry Co., Ltd.

Ford Motor Company Limited

University of Chicago

Inventec Appliances Corporation

Ambit Microsystems (shanghai) Ltd.

Montage Technology Co., Ltd.

University of Shanghai for Science and Technology

Siemens Aktiengesellschaft

Liang Zhang

Weifeng Tong

Fei Luo

Yong Wang

Xin Liu

Yuming Xie

Qian Li

Yu Zhang

Lei Zhang

Jian Li

Jun Wu

Lei Yang

Wei Zhang

Fuchun Liao

Hua Li

Yanfeng Zhang

Minhua Chen

Jian Mg Cheng

WeiBing Shang

Hao Wang

Jian Tong Li

Yu Meng Li

Hong Li

Jian Wu

Zhiqiang Li

Xin Xiao

Li Xue

Hongwen Li

Lin Nan Li

Bin Luo

Hui Wang

Jun Chen

Wei Song

Yu Chen

Ping Li

Yan Li

Xiaoyu Zhang

Ying Chu Wang

KangLing Ji

Yimin Liu

Sungsoo Chi

Lizhong Wang

Liang Hong

Chuan He

Xinyu Hu

Chaohui Yang

Jia Wang

Meng Wang

Dewei Bao

Zhongyuan Chang

Jia Che

Fusheng Zhou

Mingliang Xu

Qianli Ma

Guanghui Yang

Junhong Liu

Fanhong Kong

Mingqiang Guo

Jingui Jiang

Haonan Ye

Rendong Shi

Tong Han

Yu Peng Fan

Wei Bing Shang

En Peng Gao

Liang Yu

Jinwei Xia

Ning An

Ping Zhao

Liya Zhang

Jiaoyun Yang

Lihong Zhu

Margarita Perello

Enbo Zhou

Xun Zhang

Pengfei Hu

Yongchun Chen

Qian Xiao

Yanfang Zhang

Jun Xue

Songlin Zhuang

Qi Yang He

Xuexin Ding

Gang Yan

Sonja Scharlemann

Hartmut Kuehn

Huafeng Wen

Yunpeng Gao

Lu Chai

Linda Kim-Habermehl

Zhi Zeng

Shu Yu

Haitao Zhu

Lixin Jiang

Ming Wen

Juergen Dombrowski

Yunzhou Jin

Xiangyu He

Daoxun Wu

Wireless audio systems and methods for wirelessly communicating audio information are provided. The wireless audio system includes a first wireless transceiver and a second wireless transceiver. The first wireless transceiver includes a first communication module, a first codec, and a second communication module. The first communication module is configured to receive, from an audio source, first audio information. The first codec includes a first decoder configured to obtain second audio information by decoding the first audio information, and a first encoder configured to obtain third audio information by encoding the second audio information. The second communication module is configured to send the third audio information out. The second wireless transceiver includes a third communication module configured to receive the third audio information from the first wireless transceiver. The first communication module employs Classic Bluetooth, and the second communication module and the third communication module employ Low Energy (LE) Audio.

Wireless audio system and method for wirelessly communicating audio information

Embodiments of this application relate to the field of storage technologies, and disclose a data backup method and a terminal, to back up user data in a terminal when the terminal cannot be used. A specific solution is as follows: A terminal includes a first data partition, and the first data partition supports to start an operating system when the terminal is powered on. The terminal starts the operating system by using a second data partition after detecting a power-on failure of the terminal or detecting a preset operation of a user. The second data partition is a blank data partition. After the operating system is successfully started, the terminal transmits user data in the first data partition to a first storage medium. The first storage medium is located outside the terminal and is connected to the terminal.

User data backup to data partition of storage medium

A method for fabricating a fly-eye lens comprises the following steps: preparing a fly-eye mold () and a fly-eye base (), wherein the fly-eye mold () is provided with a hemispherical recess that matches the fly-eye base (), the bottom of the hemispherical recess is provided with a number of arrayed concave surfaces, the fly-eye base () has a hemispherical structure, mini-channels () penetrating through a spherical surface and a flat surface of the fly-eye base () are arranged inside the fly-eye base, and the arrangement of openings of the mini-channels () at the spherical surface is in consistency with that of the concave surfaces inside the fly-eye mold (); and installing the fly-eye base () in the fly-eye mold () in a fitted manner, injecting polydimethylsiloxane through the mini-channels () of the fly-eye base (), curing the polydimethylsiloxane, and removing the fly-eye base () from the fly-eye mold () to obtain the fly-eye lens.

Method for fabricating fly-eye lens

Billiard ball

A network congestion handling method includes obtaining network status information; determining, based on the network status information and an Explicit Congestion Notification (ECN) optimization model, a reference probability corresponding to recommended ECN configuration information; determining destination ECN configuration information based on the reference probability; and performing ECN marking on a packet by using the destination ECN configuration information.

Network congestion handling method, model update method, and related apparatus

A method for implementing transmission performance detection includes: after successively receiving data packets whose sequence numbers are N1 and N2, determining, by a detection apparatus, that N2 is greater than N1 and that N1 and N2 are inconsecutive; after receiving the data packet whose sequence number is N2, receiving a data packet whose sequence number is M1; and when determining N1<M1<N2 and T2−T1>=RTT, determining that the data packet whose sequence number is M1 is a retransmitted packet corresponding to an upstream packet loss, where T1 is a time for receiving the data packet whose sequence number is N2, T2 is a time for receiving the data packet whose sequence number is M1.

Data transmission performance detection

A memory includes: bit lines (BLs) extending along a first direction and word lines (WLs) extending along a second direction; a read-write control circuit and a plurality of memory modules that are arranged along the first direction, wherein each of the plurality of memory modules includes a memory array and an amplifier array that are arranged along the first direction, the memory array includes at least one memory cell, the amplifier array includes at least one amplification unit, each of the BLs is electrically connected to a first terminal of a corresponding amplification unit, and each of the WLs is electrically connected to a corresponding memory cell; a column selection circuit, wherein the column selection circuit and the read-write control circuit are located on two adjacent sides of the plurality of memory modules as a whole, respectively; m column-select lines (CSLs) extending along the first direction.

Memory

Provided are a test circuit, a test device and a test method thereof. The test circuit includes: a signal processing module configured to receive a pulse signal to be tested and output a processing signal under a control signal; a sampling module connected to the output terminal of signal processing module and configured to receive the processing signal and generate a sampling signal according to the processing signal. The sampling signal includes a first sampling pulse and a second sampling pulse, the first sampling pulse and the second sampling pulse have a pulse width difference, the pulse width difference is equal to the pulse width of the pulse signal.

Test circuit and test method thereof

A method for repairing a memory device includes: performing error detection on memory units of the memory device; temporarily storing each of unit addresses of detected error units in registers until the number of the detected error units reaches a first preset number, where the detected error units are damaged memory units, and each of the detected error unit occupies a respective one of the registers, and each of the unit addresses comprises a row address; successively selecting one of the registers as a target register; determining whether a row addresses in the target register exists in a reference storage module, where a repaired row address or an unrepaired row address is stored in the reference storage module; and repairing error units that are not repaired through the row addresses according to a result of the determination.

Method and system for repairing memory device

In certain aspects, a wireless multimedia apparatus and an operation method thereof are disclosed. The wireless multimedia apparatus includes a system on chip (SoC), including a memory configured to store code and a processor coupled to the memory. When the code is executed, the processor is configured to determine that a router is available and connected to a multimedia provider. The processor is configured to connect to the router based on configuration information associated with the router and receive multimedia data from the multimedia provider via the router. The processor is configured to determine whether the router is still available. Responsive to the router being unavailable, the processor is configured to turn on a softAP based on the configuration information associated with the router to connect to the multimedia provider via the softAP. The processor is configured to receive the multimedia data from the multimedia provider via the softAP.

Wireless multimedia apparatus and operation method thereof

A novel polymer mixture having fast drying time, and good tensile strength and elongation at break properties, a multilayer article comprising a base layer made from the polymer mixture and a top layer, and a method of preparing the multilayer article.

Polymer mixture, multilayer article containing the same, and process of preparing the multilayer article

The repair circuit is disposed in a memory including a normal memory area and a redundant memory area including a target repair unit immediately adjacent to the normal memory area, and the repair circuit being configured to control the target repair unit to repair an abnormal memory cell in the normal memory area. The repair circuit includes: a first control circuit, configured to receive signals at a target number of bits from low to high in a row address, process the received signals to obtain a control result, and output the control result, where the target number is associated with a number of Word Lines in the target repair unit; and a repair determination circuitry, connected to an output terminal of the first control circuit, and configured to receive the control result and output, in combination with the control result, a repair signal indicating whether to perform a repair operation.

Repair circuit, memory, and repair method

Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

Apparatuses and methods for pipelining memory operations with error correction coding

A testing circuit includes: a first sampling module configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the pulse signal; and a second sampling module configured to receive the pulse signal, and generate a second sampled signal according to the pulse signal. The second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the pulse signal.

Testing circuit, testing device and testing method thereof

Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of low data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to High.

Read operation circuit, semiconductor memory, and read operation method

Growing community of inventors

Shanghai, China

Liang Zhang