Micron Technology Incorporated

Liang Yu

Jonathan Scott Parry

Jeremy Binfet

Luigi Pilolli

Biagio Iorio

Walter Di Francesco

Ali Mohammadzadeh

Luca Nubile

Stephen L Miller

Chulbum Kim

Fumin Gu

John Paul Aglubat

Fulvio Rori

Daniel J Hubbard

Tal Sharifie

William C Filipiak

Xiaojiang Guo

Stephen D Hanna

Suresh Rajgopal

Jeremy Wayne Butterfield

Hojung Yun

Methods, systems, and devices for power management associated with memory and a controller are described. A memory system performs a power management operation that accounts for power usage by any combination of application specific integrated circuits (ASICs) and memory arrays. The power management operation includes multiple logical unit numbers (LUNs) assigned to a single ASIC, which increases a quantity of bits for communicating a power usage. An ASIC included in a memory system may utilize twice as many bits for communicating power usage information when compared to a NAND array. As part of the power management operation, an ASIC may transmit, to a controller, a first set of bits indicating a power usage of the ASIC, a first subset of the set of bits transmitted during a first instance of a token ring and a second subset of the set of bits transmitted during a second instance of the token ring.

Power management associated with memory and controller

A method includes receiving a request to perform a memory access operation, wherein the memory access operation includes a set of sub-operations, selecting a current quantization data structure from a plurality of current quantization data structures, wherein each current quantization data structure of the plurality of current quantization data structures maintains, for each sub-operation of the set of sub-operations, a respective current quantization value reflecting an amount of current that is consumed by the respective sub-operation based on a set of peak power management (PPM) operation parameters, and causing the memory access operation to be performed using PPM based on the current quantization data structure.

Multiple current quantization values for peak power management

A memory device includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a memory die and control logic, operatively coupled with the memory die, to perform operations including receiving, during a current auxiliary data communication cycle, a token to enable auxiliary data communication, in response to receiving the token, determining whether to communicate auxiliary data via an auxiliary data channel to at least one other memory die of a plurality of memory dies, and in response to determining to communicate the auxiliary data via the auxiliary data channel to the at least one other memory die, causing the auxiliary data to be communicated to the at least one other memory die.

Dual data channel peak power management

A memory device includes a set of memory dies, each memory die of the set of memory dies including a memory array and first control logic operatively coupled to the memory array, and an application-specific integrated circuit (ASIC) including a general-purpose input/output component (GPIO) including at least one digital pad communicably coupled to each memory die of the set of memory dies, and second control logic, operatively coupled to memory, to perform operations related to peak power management (PPM).

Peak power management extensions to application-specific integrated circuits

A memory device includes memory dies. Each memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication. The operations include monitoring a data burst with respect to the memory array, detecting a current reservation trigger associated with the data burst, in response detecting the current reservation trigger, reserving an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst, detecting a plurality of input/output cycles of the data burst following the preamble period, and in response to detecting the number of input/output cycles, reserving, based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.

Peak power management data burst communication

A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.

Peak power management priority override

A memory device might include registers configured to store expected peak current magnitudes corresponding to a plurality of memory devices containing the memory device, and a controller configured to cause the memory device to determine whether to initiate a next phase of an access operation in response to at least a first sum of an expected peak current magnitude for the next phase of the access operation in a selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a first current demand budget, and a second sum of the expected peak current magnitude for the next phase of the access operation in the selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a second, lower, current demand budget.

Power management

A memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a peak power management (PPM) token during a current PPM cycle, in response to receiving the PPM token, determining, based on a set of communication frequencies, whether to communicate auxiliary data to at least one other memory die during the current PPM cycle, wherein each communication frequency of the set of communication frequencies indicates when a respective type of auxiliary data is eligible for communication during a PPM cycle, and in response to determining to communicate auxiliary data to the at least one other memory die, causing a selected type of auxiliary data to be communicated to the at least one other memory die, wherein the selected type of auxiliary data is determined from the set of communication frequencies in view of the current PPM cycle.

Scheduled interrupts for peak power management token ring communication

A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include causing a memory die to be placed in a suspended state to suspend execution of a first media access operation with a reserved current budget, receiving a set of requests to execute at least a second media access operation during the suspended state, and in response receiving the set of requests, handling the set of requests by implementing current budget arbitration logic with respect to the reserved current budget.

Peak power management in a memory device during suspend status

A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

Prioritized power budget arbitration for multiple concurrent memory access operations

A method includes selecting a particular ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B # pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

Internal clock signaling

A memory device includes sets of memory dies. Each set of memory dies includes a memory dies associated with a respective channel of a plurality of channels, and each channel of the plurality of channels has a respective ready busy (RB) signal. The memory device further includes an input/output (I/O) expander to perform operations including receiving at least one command to perform clock synchronization associated with a clock signal with respect to the plurality of sets of memory dies, and in response to receiving the command, causing circuitry of the I/O expander to be configured to create an RB signal short with respect to a particular combination of channels. The clock synchronization is associated with peak power management (PPM) initialization.

I/o expanders for supporting peak power management

A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

Charge-sharing capacitive monitoring circuit in a multi-chip package to control power

A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

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Boise, ID, United States of America

Liang Yu