Samsung Electronics Co., Ltd.

Intel Corporation

Nvidia Corporation

Symantec Corporation

Liang Yin

Hongzhong Zheng

Chaohong Hu

Steven James Heinrich

Zvi Guz

Shirish C Gadre

Sunil Kumar

Mu-Tien Chang

Harry Muljono

Vivek Garg

Nirmal Raj Saxena

Wishwesh Anil Gandhi

Naveen Cherukuri

Mark Hairgrove

Peter C Mills

Michael Alan Fetterman

Phanindra Mannava

Manan Patel

Binata Bhattacharyya

Uksong Kang

Karan Mehra

Gentaro Hirota

Martin Stich

Praveen Joginipally

Vaishali Kulkarni

Chandra P Joshi

Chung-Chi Wang

Adam Hendrickson

David Charles Patrick

Sandeep Navada

Saurabh Hukerikar

Sujoyita Kaushikkar

Alex Kuperman

Zvika Guz

Abhijeet Ghadge

Sami Olavi Johannes Kiminki

Daniel Glenn Robinson

Anup Holey

Alexander Michael Waterman

Jeff Smith

Paul Racunas

Yiyang Feng

A processing device including a first cache is coupled to a system memory and a parallel processing unit (PPU) including a second cache. An operation to modify cache lines of the second cache associated with a first aperture of the system memory is received. A first subset of cache lines of the second cache is identified. The first subset of cache lines is associated with the first aperture of the system memory and is different from a second subset of cache lines of a second aperture of the system memory. The first subset of cache lines is modified as specified by the cache operation.

Systems and methods for aperture-specific cache operations

Various embodiments include techniques for managing cache memory in a computing system. The computing system includes a sectored cache memory that provides a mechanism for software applications to directly invalidate data items stored in the cache memory on a sector-by-sector basis, where a sector is smaller than a cache line. When all sectors in a cache line have been invalidated, the cache line is implicitly invalidated, freeing the cache line to be reallocated for other purposes. In cases where the data items to be invalidated can be aligned to sector boundaries, the disclosed techniques effectively use status indicators in the cache tag memory to track which sectors, and corresponding data items, have been invalidated by the software application. Thus, the disclosed techniques thereby enable a low-overhead solution for invalidating individual data items that are smaller than a cache line without additional tracking data structures or consuming additional memory transfer bandwidth.

Cache memory with per-sector cache residency controls

According to one general aspect, an apparatus may include a memory module. The memory module may include a plurality of memory banks configured to store data. The memory module may include a plurality of memory bank power down controllers, each configured to place one or more respective memory bank(s) in a power down mode. The memory module may include a memory module command interface configured to receive a handshake command from a memory controller, wherein the handshake command comprises a command to remove an indicated memory bank from power down mode.

Fine grain level memory power consumption control mechanism

Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

Error containment for enabling local checkpoint and recovery

A computing system including: a host interface configured to parse a command packet from a command address medium; and a command block, coupled to the host interface, configured to: assemble a command from the command packet.

Computing system with communication mechanism

A computing system includes: a host memory including a driver and an address map; a host central processing unit, coupled to the host memory, configured to divide a command to a command packet with the driver, map the command packet to the address map, and deliver the command packet based on the address map over a command address medium.

Computing system with communication mechanism and method of operation thereof

A memory device includes a memory, a data interface, an error interface and a controller. The data interface communicates data to and from the memory device through an external main memory path. The error interface communicates error information from the memory device through an external system control path and that is separate from the main memory path. The controller is coupled to the data interface, the error interface, and the memory. The controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the memory and generates corrected data by encoding data written to the memory and decoding data read from the memory, generates error information, transmits the corrected data through the data interface, and transmits the error information through the error interface. The ECC controller records the error information in response to the ECC engine.

Memory devices and modules

A memory system includes a master controller, an interface with a host computer, and a link bus configured to couple with a slave controller. The master controller includes an address mapping decoder, a transaction queue, and a scheduler. The address mapping decoder is configured to decode address mapping information of a memory device coupled to the slave controller. The scheduler of the master controller is configured to reorder memory transaction requests received from the host computer in the transaction queue using the address mapping information of the memory device. The memory system employs an extended open page policy based on the pending memory transaction requests in the transaction queue of the master controller.

High performance transaction-based memory systems

A Processing-In-Memory (PIM) model in which computations related to the POPCOUNT and logical bitwise operations are implemented within a memory module and not within a host Central Processing Unit (CPU). The in-memory executions thus eliminate the need to shift data from large bit vectors throughout the entire system. By off-loading the processing of these operations to the memory, the redundant data transfers over the memory-CPU interface are greatly reduced, thereby improving system performance and energy efficiency. A controller and a dedicated register in the logic die of the memory module operate to interface with the host and provide in-memory executions of popcounting and logical bitwise operations requested by the host. The PIM model of the present disclosure thus frees up the CPU for other tasks because many real-time analytics tasks can now be executed within a PIM-enabled memory itself. The memory module may be a Three Dimensional Stack (3DS) memory or any other semiconductor memory.

In-memory popcount support for real time analytics

A computing system includes: a write buffer block configured to: receive a data in a write buffer entry for staging the data prior to transferring the data to a storage cell, determine a validity identification of the data for a buffer entry address of the write buffer entry, store the data based on the validity identification to the write buffer entry, and a memory computing block, coupled to the write buffer block, configured to read the data for accessing the write buffer block.

Computing system with write buffer including speculative storage write and method of operation thereof

A computing system includes: a memory computing block configured to: identify a partial data computing (PDC) command, a data mask, a partial data, or a combination thereof based on decoding a data packet, compute a computation result for identifying a portion of a read data to be modified according to the PDC command, the data mask, the partial data, or a combination thereof, generate a merge result based on modifying the portion of the read data according to the computation result, and a memory interface, coupled to the memory computing block, configured to transmit the merge result.

Computing system with partial data computing and method of operation thereof

Embodiments of the inventive concept include a volatile memory device including a memory cell array, the memory cell array including multiple rows and/or banks to store data. The memory device can include an address decoder coupled to the memory cell array. The memory device can include a control logic section coupled to the address decoder. The control logic section can include a defresh logic section configured to intentionally violate, by an activate command, a row precharge time (T) and/or a row active time (T) for each of the plurality of rows to clean the data from the memory cell array. Memory data can be cleaned from the memory cell array responsive to the violations.

Volatile memory self-defresh

In one embodiment, the present invention includes a receiver having a delay lock loop (DLL) to receive a clock signal and to generate a plurality of clock phases therefrom, and an offset controller including a first register set for a first phase interpolator and a second register set for a second phase interpolator. At initiation of a track pre-tune process, both phase interpolators are controlled to generate sampling signals at a common clock phase. Other embodiments are described and claimed.

Unidirectional sweep training for an interconnect

A number of caching agents are interconnected by a ring. A number of trackers of a home agent are pre-allocated to each of the number of caching agents. A tracker provides a permit for a caching agent to issue a request to the home agent. In case a caching agent needs to issue more requests to the home agent, the caching agent may borrow a tracker from another caching agent by sending a message via the ring to other caching agents. A caching agent receiving the borrowing message may either respond the borrowing message by lending a tracker pre-allocated to the corresponding caching agent, or deny the borrowing request by forwarding the borrowing message to another caching agent.

Allocation of tracker resources in a computing system

A system and method for determining a designated boot volume of a computer system coupled to a SAN is disclosed. The computer system is configured to boot from a logical volume on the SAN using a corresponding bus interface. One or more logical volumes within the SAN are identified and have code written to them. The code is executable to determine whether or not the computer system is configured to boot from that logical volume and to determine configuration information stored on the identified logical volumes.

Hardware-independent detection of SAN logical volumes

Growing community of inventors

San Jose, CA, United States of America

Liang Yin