Yangtze Memory Technologies Co., Ltd.

Liang Xiao

He Chen

Shu Wu

Yong Qing Wang

Zi Qun Hua

Jin Wen Dong

Li Hong Xiao

Jifeng Zhu

Ziqun Hua

Meng Yan

Jian Xu

Yongqing Wang

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes preparing a stacked device having a first array device and a second array device, forming an opening on a back side of the second array device, and forming one or more contact pads in the opening. The first array device includes first front pads on a face side of the first array device and first back pads on a back side of the first array device. The second array device includes second front pads on a face side of the second array device and bonded with the first back pads. The one or more contact pads are disposed at a level proximate to the second front pads with respect to the first array device.

Contact pads of three-dimensional memory device and fabrication method thereof

A memory device includes a memory array, disposed on a substrate of a peripheral-circuit structure; a conductive plug, extending through the memory array and connected to the peripheral-circuit structure; and a conductive pad layer, disposed over the memory array and including a plurality of conductive pads spaced apart from each other. The conductive plug protrudes into a corresponding conductive pad of the plurality of conductive pads.

Memory device and fabrication method thereof

A semiconductor device is provided. The semiconductor device includes a base layer having a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device includes a stack of alternating word line layers and insulating layers that is positioned over the first side of the base layer, where the stack includes a first region and a second region. A channel structure extends through the first region of the stack in a vertical direction and further extends into the base layer from the first side. A plurality of connection structures are formed over the second side of the base layer and include a first connection structure that is coupled to the channel structure.

Three-dimensional NAND memory device and method of forming the same

A fabricating method of a semiconductor device is provided. A temporary semiconductor structure is provided. The temporary semiconductor structure includes a temporary substrate and a conductive layer, the temporary substrate has a first surface, the conductive layer is disposed on the first surface of the temporary substrate, and the conductive layer includes one or more first trace. Then, a recess is formed in the temporary semiconductor structure to form a first semiconductor structure and a first substrate. The recess penetrates through the first substrate and expose the one or more first trace. Thereafter, an input/output pad is formed in the recess and on the one or more first trace.

Fabricating method of semiconductor device with exposed input/output pad in recess

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a semiconductor structure and an input/output pad. The semiconductor structure includes a first substrate and a conductive layer, in which the first substrate has a first surface and a second surface opposite to each other, the conductive layer is disposed on the first surface of the first substrate, and the conductive layer includes one or more first trace. The first semiconductor structure has a recess penetrating the first substrate and exposing the one or more first trace, and the input/output pad is disposed on the one or more first trace and in the recess.

Semiconductor device with exposed input/output pad in recess

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first die and a second die boned face-to-face. The first die includes first transistors formed on a face side of the first die in a semiconductor portion and at least a contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a substrate and second transistors formed on a face side of the second die. Further, the semiconductor device includes a first pad structure disposed on a back side of the first die and the first pad structure is conductively coupled with the contact structure. An end of the contact structure protrudes from the insulating portion into the first pad structure. Further, in some embodiments, the semiconductor device includes a connection structure disposed on the back side of the first die and conductively connected with the semiconductor portion.

Pad structures for semiconductor devices

The present disclosure provides a method of fabricating a semiconductor device. The method can include bonding a first die and a second die face to face, the first die including a substrate, transistors formed on a face side of the first die over a semiconductor layer with an insulating layer between the substrate and the semiconductor layer, and a first contact structure on the face side of the first die extending through the insulating layer. The method can also include exposing the first contact structure from the back side of the first die, forming, from the back side of the first die, a contact hole in the insulating layer to expose the semiconductor layer, and forming, on the back side of the first die, a first pad-out structure connected with the first contact structure and a second pad-out structure, on the contact hole, conductively connected with the semiconductor layer.

Pad-out structure for semiconductor device and method of forming the same

A method for forming a dual damascene interconnect structure. A substrate having a conductor layer, an etch stop layer on the conductor layer, a dielectric stack on the etch stop layer, and a hard mask layer on the dielectric stack is provided. A photoresist layer having a resist opening is formed on the hard mask layer. The hard mask layer is etched through the resist opening to form a hard mask opening. The dielectric stack is etched through the hard mask opening to form a partial via hole. The photoresist layer is trimmed to form a widened resist opening above the partial via hole. The hard mask layer is etched through the widened resist opening to form a widened hard mask opening above the partial via hole. The dielectric stack is etched through the widened hard mask opening and the partial via hole to form a dual damascene via.

Method for forming dual damascene interconnect structure

A memory structure provided by this invention includes a first substrate, a dielectric layer, a bonding pad, and an isolation structure. The first substrate includes a substrate layer and a memory layer. The substrate layer has opposite first and second surfaces, the memory layer is located on the first surface of the substrate layer, and the first substrate includes a bonding pad region. The dielectric layer is disposed on the second surface of the substrate layer. The bonding pad is disposed on the surface of the dielectric layer in the bonding pad region. The isolation structure penetrates through the substrate layer and is disposed at the edge of the bonding pad region and surrounds the substrate layer in the bonding pad region, and the isolation structure is used for isolating the substrate layer in the bonding pad region from the substrate layer at the periphery of the isolation structure.

Growing community of inventors

Wuhan, China

Liang Xiao