Apple Inc.

Liang Xia

Terence M Potter

Benjiman L Goodman

Andrew M Havlir

Robert D Kenney

Brian K Reynolds

Mario A Maldonado, Jr

A data queuing and format apparatus is disclosed. A first selection circuit may be configured to selectively couple a first subset of data to a first plurality of data lines dependent upon control information, and a second selection circuit may be configured to selectively couple a second subset of data to a second plurality of data lines dependent upon the control information. A storage array may include multiple storage units, and each storage unit may be configured to receive data from one or more data lines of either the first or second plurality of data lines dependent upon the control information.

Data alignment and formatting for graphics processing unit

Techniques are disclosed relating to clause-based execution of program instructions, which may be single-instruction multiple data (SIMD) computer instructions. In some embodiments, an apparatus includes execution circuitry configured to receive clauses of instructions and SIMD groups of input data to be operated on by the clauses. In some embodiments, the apparatus further includes one or more storage elements configured to store state information for clauses processed by the execution circuitry. In some embodiments, the apparatus further includes scheduling circuitry configured to send instructions of a first clause and corresponding input data for execution by the execution circuitry and indicate, prior to sending instruction and input data of a second clause to the execution circuitry for execution, whether the second clause and a first clause are assigned to operate on groups of input data corresponding to the same instruction stream. In some embodiments, the apparatus is configured to determine, based on the indication, whether to maintain as valid, for use by the second clause, stored state information for the first clause.

Clause chaining for clause-based instruction execution

A novel set of reconfiguration tools combine the RTL (Register Transfer Language) construct detection of synthesis compilers with a more advanced implementation of expansion syntax. HDL (Hardware Description Language) coding constructs are automatically detected and recoded and/or modified, for both behavioral and structural HDL code. Configuration file(s) may be used to define the transformations, and transformation commands within the configuration file(s) may define where and how to apply RTL changes. The tool may automatically identify sections of code as the file is parsed (e.g. like a compiler). The transformations are written out in RTL, and the resulting reconfigured RTL file(s) may be processed by a synthesis tool, or may be simulated using a suitable simulator. This allows for automated detection and configurable modification of HDL-coding constructs. Design changes may therefore be verified earlier in the design process, since changes are embedded in RTL, instead of being embedded in the netlist.

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Austin, TX, United States of America

Liang Xia