Realtek Semiconductor Inc.

Liang-Wei Huang

Shieh-Hsing Kuo

Hsuan-Ting Ho

Ta-Chin Tseng

Ching-Yao Su

Sheng-Fu Chuang

Chih-Yung Shih

Ting-Fa Yu

Chi-Shun Weng

Hsuan-ting Ho

Yuan-Jih Chu

Ming-Feng Hsu

Shih-Hsiung Huang

Chun-Hung Liu

Shih-Wei Wang

Shih-hsiung Huang

Li-Han Liang

Yu-Xuan Huang

Chien-Sheng Lee

Yan-Guei Chen

Chia-Lin Chang

Yun-Tse Chen

Chi-Hsi Su

Tzu-Han Hsu

Ming-Je Li

Li-Wei Fang

Heng Cheong Lao

Tsung-Cheng Lee

Kuei-Ying Lu

Yang-Bang Li

Chun-Wen Yeh

Cheng-Han Lee

Kai-Wen Cheng

Liang-Huan Lei

Meng-Han Hsieh

Ming-Chieh Cheng

Shian-Ru Lin

Kai-Yue Lin

Mei-Chao Yeh

Su-Liang Liao

Jiun-Hung Yu

Po-Han Lin

Chih-Chi Wang

Chieh-Sheng Lee

Yao-Yi Tsai

Chia-Min Li

Hsin-Yu Lue

Yun-Chih Tsai

Tsung-Chen Wu

Chih-Lung Chen

Chun-Yu Chen

Jie-Fan Lai

Wei-Jyun Wang

Sheng-Hsiung Lin

Hui-Min Huang

Yi-Huei Lei

Chih-Jung Chiang

Rong-Jen Chang

Tai-Yi Huang

Chi-Sheng Hsu

Lie-Way Fang

Mei-chao Yeh

Lie-Wei Fang

Chin-Chi Yang

Shi-Ming Lu

Po-Hsiu Hsiao

Chia-lin Chang

Tzung-hua Tsai

Wei-Chiang Hsu

Wan-Chun Huang

Huan-Chung Chen

Chung-Wen Tang

Lie Way Fang

Hsiao-Ming Huang

Fang-Ru Wang

Wen-Jen Cho

Jui-Yi Liu

A signal receiver and a slicer are capable of mitigating the static mismatch error of a far-end digital-to-analog converter. The slicer includes an adjustable slicing circuit and an error signal generating circuit. The adjustable slicing circuit determines which of (N+1) signal levels is corresponding to an input signal according to N slicer levels and thereby outputs an output signal, wherein the input signal is originated from the far-end digital-to-analog converter. The adjustable slicing circuit further adjusts at least some of the (N+1) signal levels according to an error signal and adjusts at least some of the N slicer levels, wherein the N is an integer greater than two. The error signal generating circuit is coupled to the adjustable slicing circuit and generates the error signal according to the input and output signals.

Signal receiver and slicer

The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit. The echo calibration circuit makes response coefficients converge according to the error signal and pseudo-noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates codeword offset table according to the offset.

Digital-to-analog conversion apparatus and method having signal calibration mechanism

The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism. A DAC circuit includes conversion circuits to generate an output analog signal and an echo-canceling analog signal. An echo transmission circuit performs signal processing on an echo path to generate an echo signal. An echo calibration circuit includes odd and even calibration circuits to perform mapping according to offset tables and perform processing according to response coefficients on odd and even input parts of an input digital signal to generate odd and even calibration parts of an echo-canceling calibration signal. A calibration parameter calculation circuit generates offsets according to an error signal between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration circuit. The echo calibration circuit makes the coefficients converge according to the error signal and pseudo noise transmission path information, and updates the offset tables according to the offset.

The present invention discloses a digital-to-analog conversion apparatus having current source measuring mechanism. A digital-to-analog conversion circuit in turn sets one of thermo-controlled current sources as an initial current source to operate according to two specific input codewords included in an input digital signal to generate an output analog signal. The values of the output analog signal corresponding to the two specific input codewords have opposite signs and the same absolute value. An echo transmission circuit processes the output analog signal to generate an echo signal. An echo-canceling circuit processes the input digital signal according to echo-canceling coefficients to generate an echo-canceling signal and receives an error signal to converge the echo-canceling coefficients. A current calculating circuit generates converged coefficients statistics values and perform calculation thereon with a predetermined inverse matrix to generate a current amount of each of the thermo-controlled current sources. An error calculation circuit subtracts the echo signal and the echo-canceling signal to generate the error signal.

Digital-to-analog conversion apparatus having current source measuring mechanism and current source measuring method of the same

A digital-to-analog converter circuit generates an analog transmitted signal according to a digital transmitted signal. A first echo canceller circuit generates a first echo cancelling signal according to the digital transmitted signal. A processor circuit generates an analog processed signal according to the analog transmitted signal, the first echo cancelling signal, and a received signal. An analog-to-digital converter circuit generates a digital value according to the analog processed signal and two slicer levels of a plurality of slicer levels. A storage circuit stores a look-up table. The look-up table records an offset value corresponding to the digital value. The storage circuit further outputs a first output signal according to the digital value and the offset value. The offset value is updated according to an error value associated with the first output signal.

Echo cancelling system and echo cancelling method

The present invention discloses a signal gain tuning circuit having adaptive mechanism. An amplifier receives an analog signal to generate a tuned analog signal to an ADC circuit to further generate a digital signal. A gain control capacitor array and the amplifier together determine a gain of the tuned analog signal. The control circuit receives an actual level of the digital signal to determine an offset of the digital signal and an estimated level to generate a tuning control signal. Each of coarse-tuning capacitors of a coarse-tuning capacitor array corresponds to a first tuning amount relative to a maximal gain. Each of fine-tuning capacitors of a fine-tuning capacitor array corresponds to a second tuning amount relative to the maximal gain. A tuning capacitor enabling combination of the coarse-tuning and fine-tuning capacitor arrays are determined according to the tuning control signal to tune the gain and decrease the offset.

Signal gain tuning circuit and method having adaptive mechanism

A calibrating device can mitigate the static mismatch error of a digital-to-analog converter (DAC), and includes a digital code generating circuit, the DAC, an analog-to-digital converter (ADC), a filter circuit, an indicating circuit, and a statistical circuit. The digital code generating circuit generates a digital code of N digital codes. The DAC generates an analog signal corresponding to one of N signal levels according to the digital code. The ADC generates a digital signal according to the analog signal. The filter circuit generates a gradient value according to the difference between the digital code and the digital signal. The indicating circuit generates a selection signal according to the digital code. The statistical circuit learns from the selection signal that the gradient value is corresponding to a Kdigital code of the N digital codes, and determines whether the Kdigital code should be adjusted according to the gradient value.

Calibrating device for digital-to-analog conversion

The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.

Digital-to-analog conversion circuit and method having signal calibration mechanism

The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

A method for cancelling radio frequency interference (RFI) and a communication system thereof are provided. In the communication system, digital signals of a frequency domain are converted from analog signals and received by the communication system generally carry RFI, and the signals are processed by an equalizer and a far-end crosstalk canceller. Then, for preventing erroneous signals from forming due to an occurrence of a notch, masking parameters applied to the equalizer and the far-end crosstalk canceller are modified for not processing frequency bands that are RFI-affected. The frequency bands can be ignored by masking corresponding bins in the frequency domain after a fast Fourier transformation. The signals processed by the equalizer and the far-end crosstalk canceller are then outputted to an RFI canceller, and the signals with RFI cancellation can be obtained.

Method for cancelling radio frequency interference and communication system thereof

The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

A method includes: generating a first signal according to a digital signal; filtering the first signal according to first filter coefficients of first filter to generate a second signal; adding a first reference signal with the second signal to generate a third signal; performing digital-to-analog conversion according to the first and third signals to generate and output an echo signal; performing analog-to-digital conversion according to the echo signal to generate a fourth signal; generating a fifth signal according to the digital signal and the fourth signal; and updating the first filter coefficients according to the fifth signal. Generating the fifth signal includes: generating second filter coefficients of second filter; updating the second filter coefficients according to a second reference signal and the fourth signal; obtaining a first and second representative coefficients of the second filter coefficients; and generating the fifth signal according to the first and second representative coefficients.

Analog echo cancelation method

An Ethernet physical-layer circuit corresponding to a first port is connected to a first link partner device through the first port and a first Ethernet cable. The Ethernet physical-layer circuit and other physical-layer circuits all employ an output oscillation signal of a crystal oscillator to respectively generate clock waveforms, and they are configured in a master mode when the crosstalk noise is converged and compensated.

Ethernet transceiver device and ethernet physical-layer circuit

A signal transceiver circuit, a method of operating a signal transmitting circuit, and a method of setting a delay circuit are provided. The signal transceiver circuit is used to send an output signal and receive an input signal, and includes: a delay circuit for delaying a first clock to generate a second clock; a first digital-to-analog converter (DAC) for converting a first digital signal into the output signal according to the first clock; a second DAC for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter (ADC) for converting the analog signal into a second digital signal.

Signal transceiver circuit, method of operating signal transmitting circuit, and method of setting delay circuit

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Hsinchu, Taiwan

Liang-Wei Huang