Texas Instruments Corporation

Liang Wan

Yiqi Tang

Rajen Manicon Murugan

Makarand Ramkrishna Kulkarni

Jie Chen

Osvaldo Jorge Lopez

Jonathan Almeria Noquil

Christopher Daniel Manack

Michael G Amaro

Hiep Xuan Nguyen

William Todd Harrison

Manu Joseph Prakuzhy

Vivek Swaminathan Sridharan

Naweed Anjum

Steven Alfred Kummerl

A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

Multi-layer semiconductor package with stacked passive components

In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

Plated metal layer in power packages

An antenna in package (AIP)includes an IC dieincluding bond padsand a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layerincluding a top dielectric layer, a top metal layerincluding an antenna, and a bottom layerincluding a bottom dielectricand a bottom metal layerincluding contact pads including a first contact pad, and filled vias. The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillarare electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.

Antenna in package having antenna on package substrate

A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

Semiconductor package with shunt and patterned metal trace

A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

Semiconductor package with electromagnetic interference shielding

A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

Integrated system-in-package with radiation shielding

In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

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Liang Wan