International Business Machines Corporation

Liang-Teck Pang

Phillip John Restle

William Robert Reohr

Thomas J Bucelot

Jente Benedict Kuang

Joel Abraham Silberman

Kevin John Nowka

Jason D Hibbeler

Alan J Drake

Michael G R Thomson

Gary Dale Carpenter

Robert Allen Groves

Yong I Kim

Jae-Joon Kim

Yu-Shiang Lin

Eren Kursun

Matthew R Wordeman

Robert Louis Franch

Jerry C Kao

Dureseti Chidambarrao

Hung Cai Ngo

Amith Singhee

Fadi Hikmat Gebara

Gregory Scott Still

Emrah Acar

Aditya Bansal

Yong Liu

Joshua D Friedrich

Jayakumaran Sivagnaname

A method for providing a stitchable clock mesh, a dual operation mode system, and a method for providing a master clock stratum are, in turn, provided for a 3D chip stack having two or more strata. The method for providing a stitchable clock mesh includes providing, by at least one clock mesh disposed on each stratum and having multiple sectors, a global clock signal to various chip locations. The method further includes collecting, by mesh data sensors on each stratum, mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The method also includes selectively performing, by joining circuitry, a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.

Stitchable global clock for 3D chips

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

Tunable sector buffer for wide bandwidth resonant global clock distribution

A stitchable clock mesh, a dual operation mode method, and a master clock stratum are provided for a 3D chip stack. The stitchable clock mesh includes at least one clock mesh, on each of the two or more strata, having a plurality of sectors for providing a global clock signal. The stitchable clock mesh further includes mesh data sensors, on each of the two or more strata, for collecting mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The stitchable clock mesh further includes mesh segmentation and joining circuitry for selectively performing a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan.

Distributed phase detection for clock synchronization in multi-layer 3D stacks

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Wide bandwidth resonant global clock distribution

A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

Circuit technique to electrically characterize block mask shifts

There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.

Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.

Defect detection on characteristically capacitive circuit nodes

Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Changing resonant clock modes

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, at least one inductor, at least one tunable resistance switch, and a capacitor network. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Variable resistance switch for wide bandwidth resonant global clock distribution

There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.

AC supply noise reduction in a 3D stack with voltage sensing and clock shifting

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.

3D chip stack skew reduction with resonant clock and inductive coupling

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

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White Plains, NY, United States of America

Liang-Teck Pang