Sun Microsystems, Inc.

Oracle America, Inc.

Liang T Chen

David R Emberson

Thomas M McWilliams

Earl T Cohen

Michael W Parkin

Derek E Pappas

William Kwei-Cheung Lam

Jeffrey B Rubin

Jeffrey M Broughton

Ashley N Saulsbury

David S Allison

Ankur Narang

Ihao Chen

Michael S Ball

Keith H Bierman

Oyekunle A Olukotun

James B Burr

Yuan Lin

Nyles I Nettleton

Christopher D Quenelle

Cristina N Cifuentes

Donald J Kretsch

Deepankar Bairagi

A method for executing an application, that includes instantiating, by a first thread, a first executable object and a second executable object, creating a first processing unit and a second processing unit, instantiating an executable container object, spawning a second thread, associating the first executable object and the second executable object with the executable container object, processing the executable container object to generate a result, and storing the result. Processing the executable container object includes associating the first executable object with the first processing unit, and associating the second executable object with the second processing unit, wherein the first thread processes executable objects associated with the first processing unit, wherein the second thread processes executable objects associated with the second processing unit, and wherein the first thread and the second thread execute concurrently.

Method and system for concurrently executing an application

A method for dispatching a remote debugging agent (RDA), involving embedding the RDA in a target program to obtain a remotely debuggable target program, submitting the remotely debuggable target program to a distributed computing environment, wherein the distributed computing environment includes a plurality of nodes, executing the remotely debuggable target program on at least one of the plurality of nodes, establishing a connection between the RDA and a central debugging tool, and debugging the remotely debuggable target program using the central debugging tool.

Method and apparatus for dispatching a remote debugging agent in a distributed computing environment

A method for compiling a logic design includes inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, compiling separately the plurality of modules into a plurality of object files, and linking the plurality of object files to execute the logic design.

Compiling and linking modules of a cycle-based logic design

A method and apparatus for cycle-based simulation of a transparent latch includes classifying a phase of the transparent latch, classifying a phase of an input to the transparent latch, and classifying a phase of a simulation cycle. The transparent latch is simulated as a cycle-based simulation element based on the phase of the transparent latch, the phase of the input to the transparent latch, and the phase of the simulation cycle.

Method and apparatus for simulating transparent latches

A method of providing ad hoc verification for a simulation includes generating a cumulative record of a state value for the simulation of a circuit design, comparing the cumulative record of the state value to a golden record of the state value to obtain a comparison result, and performing ad hoc verification of the circuit design using the comparison result.

Method for providing cycle-by-cycle ad HOC verification in a hardware-accelerated environment

A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.

Method and apparatus for accelerated post-silicon testing and random number generation

A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

Method and apparatus for simulation system compiler

A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.

Method and apparatus for evaluating logic states of design nodes for cycle-based simulation

A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Method and apparatus for simulation processor

A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Method and apparatus for cycle-based computation

A system and method for generating design constraints for a logic synthesized block from timing analysis of the block. A timing analysis of logic described in software is performed for each of various operating modes of a circuit in which the logic is used. Timing data is extracted from the timing analysis and used as design constraints in the synthesis of the logic for the block.

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Saratoga, CA, United States of America

Liang T Chen