Qualcomm Incorporated

Liang Li

Andrew Evan Gruber

Elina Kamenetskaya

Guofang Jiao

Javier Ignacio Girado

Yunshan Kong

Vineet Goel

Jay Chunsup Yun

Lin Chen

Jonathan Wicks

Chunhui Mei

Samuel Benjamin Holmes

Usame Ceylan

Juraj Obert

Gregory Steve Pitarys

Balaji Calidas

Jeffrey Leger

Ruihao Zhang

Scott William Nolan

Vijay Ganugapati

Xujie Zhang

Zhenyu Qi

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for single pass anti-ringing clamping enabled image processing. A graphics processor may perform a filtering operation on a set of texture samples. The graphics processor may select, during a single sampling operation, a minimum value and a maximum value associated with the set of texture samples during the performance of the filtering operation on the set of texture samples. The graphics processor may adjust, during the single sampling operation, a value of a filtered texture sample associated with the set of texture samples based on the minimum value and the maximum value. The graphics processor may output an indication of the adjusted value of the filtered texture sample.

Single pass anti-ringing clamping enabled image processing

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may obtain a first indication of a first image including a set of first image sections with a plurality of first subsections and a second indication of a second image including a set of second image sections with a plurality of second subsections. The apparatus may also compare one first image section with one second image section. Further, the apparatus may calculate a magnitude of difference between one first subsection and each of the multiple second subsections. The apparatus may also output a third indication of at least one of: (1) a lowest magnitude of difference between the one first subsection and each of the multiple second subsections or (2) a set of coordinates for a second subsection that corresponds to the lowest magnitude of difference.

Block matching window search instruction using a graphics processing unit (GPU) texture pipeline

The present disclosure relates to methods and apparatus for mapping a source location of input data for processing by a graphics processing unit. The apparatus can configure a processing element of the graphics processing unit with a predefined rule for decoding a data source parameter for executing a task by the graphics processing unit. Moreover, the apparatus can store the parameter in local storage of the processing element and configure the processing element to decode the parameter according to the at least one predefined rule to determine a source location of the input data and at least one relationship between invocations of the task. The apparatus can also load, to the local storage of the processing element, the input data from a plurality of memory addresses of the source location determined by the parameter. A one logic unit can then execute the task on the loaded input data.

Methods and apparatus for mapping source location for input data to a graphics processing unit

The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may modify at least one texture memory object to support a data structure for one or more tensor objects. The apparatus may also determine one or more supported memory layouts for the one or more tensor objects based on the modified at least one texture memory object. Additionally, the apparatus may access data associated with the one or more tensor objects based on the one or more supported memory layouts, the data for each of the one or more tensor objects corresponding to at least one data instruction. The apparatus may also execute the at least one data instruction based on the accessed data associated with the one or more tensor objects.

Methods and apparatus for tensor object support in machine learning workloads

The present disclosure relates to methods and apparatus for configuring a texture filtering logic unit for deep learning operation. The apparatus can map one or more inputs of a deep learning operation to a respective input of a texture filtering logic unit in a graphics pipeline. Moreover, the apparatus can generate, by the texture filtering logic unit, at least one output for the deep learning operation based on the one or more inputs mapped to the texture filtering logic unit. Furthermore, the apparatus can communicate the at least one output to a programmable shader, which can analyze the output result to determine information relating to an input image based on the deep learning operation.

Methods and apparatus for configuring a texture filter pipeline for deep learning operation

The present disclosure relates to methods and apparatus for graphics processing. In some aspects, the apparatus selects a first mip-map layer with a first texture size and a second mip-map layer with a second texture size based on a third texture size of an image. The apparatus also determines a relative distance associated with the texture sizes. Additionally, the apparatus determines a first quantity of samples to select from the first mip-map layer, and determines a second quantity of samples to select from the second mip-map layer, the second quantity of samples being less than the first quantity of samples, and a second quantity of filter taps being less than a first quantity of filter taps. Also, the apparatus generates the image at the third texture size through filtering based on the first quantity of samples and the second quantity of samples.

Methods and apparatus to facilitate adaptive texture filtering

Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.

Multi-step texture processing with feedback in texture unit

A texture unit of a graphics processing unit (GPU) may receive a texture data. The texture unit may receive the texture data from the memory. The texture unit may also multiply, by a multiplier circuit of the texture unit, the texture data by at least one constant, where the constant is not associated with a filtering operation, and where the texture data comprises at least one texel. The texture unit may also output, by the texture unit, a result of multiplying the texture data by the at least one constant.

Constant multiplication with texture unit of graphics processing unit

A method and manufacture for graphics processing in which a first line of raw Bayer data and a second line of raw Bayer data are received. Each two-by-two array of a plurality of non-overlapping two-by-two arrays of the first line of raw Bayer data and the second line of raw Bayer data is mapped as a separate corresponding texel to provide a plurality of texel. At least one operation is performed on at least one of the plurality of texels.

Graphics processing unit with bayer mapping

This disclosure describes techniques for performing high order filtering in a graphics processing unit (GPU). In examples of the disclosure, high order filtering may be implemented on a modified texture engine of a GPU using a single shader instruction. The modified texture engine may be configured to fetch all source pixels needed for the high order filtering and blend them together with pre-loaded filtering weights.

High order filtering in a graphics processing unit

This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.

Dynamic pipeline for graphics processing

An example method of filtering in a graphics processing unit (GPU) may include storing, by a texture engine of the GPU, filter coefficients of a filter as a texture memory object (TMO) in a texture cache of the GPU in response to a first instruction. The method may include retrieving, by the texture engine, filter coefficients from the texture cache in response to a second instruction. The method may include storing, by the texture engine, pixel data in the texture cache of the GPU in response to the second instruction. The pixel data may include one or more pixel values. The method may include filtering, by the texture engine, the pixel data stored in the texture cache using the retrieved filter coefficients.

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San Diego, CA, United States of America

Liang Li