Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Micron Technology Incorporated

Exxonmobil Chemical Patents Inc.

Huawei Technologies Co., Limited

Intel Corporation

Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Shanghai Jiao Tong University

Other

Via Technologies, Inc.

Hand Held Products, Inc.

East China University of Science and Technology

China Unionpay Co., Ltd.

Advanced New Technologies Co., Ltd.

Liang Li

Ming Hsi Wang

Ke Zhang

Xuan Tian

Jiahui Yuan

Yu Zhang

Chao Xu

Narayanaswami R Dharmarajan

Loc Tu

Yan Li

Yanli Zhang

Dong Pan

Yuan He

Wei Zhang

Henry Chin

Jun Wan

John Wakefield Brothers

Erik Van Horn

Ke Han

Xun Wang

Boris Prokopenko

Toshiaki Yamaguchi

Yuanfeng Wang

Li-Te Kuo

Xiang Yang

Patrick Brant

Peijun Jiang

John Robert Hagadorn

Alan David Bennett

Jun Wu

Lei Li

Wei Zhao

Bo Wang

Michiaki Sano

Bin Zhao

Ming Wang

Bin Du

Vincent Yin

Jan Kalfus

Felix M Zacarias

Qin Zhen

Minna Li

Yao Jun Du

Yichen Wang

Nikhil Banwaskar

Qianqian Yu

Wen-Chung Chen

Jun Tong

Xiaodong Cai

Yingying Zhu

Xiaohua Liu

Jiangming Xu

Yin Lu

Manxia Liu

Chang Xu

Xiaohu Liu

Anubhav Khandelwal

Shih-Chung Lee

Peng Zhang

Yi He

Hua-Ling Cynthia Hsu

Shuo He

Linlin Wang

Muhammad Masuduzzaman

Yang He

Eric Paul Jourdain

Akihiro Tobioka

Fanglin Zhang

Jian Shen

Chao Gao

Ming Zhou

Koichi Ito

Peng Huang

Kang Chung Liu

Boyan Zhang

Chin-Yi Chen

Haizheng Tang

Kazuto Watanabe

Xing Fan

Yi Ping Ni

Pengfei Gao

Hiroshi Sasaki

Xiaojia Jia

Jie Lin

Takashi Yamaha

Chuan Yang

Kai Guo

Juan Liu

Katsuya Kato

Xiaofeng Huang

Shanshan Zhang

Jianbin Zheng

Ikue Yokomizo

Ryo Hiramatsu

Hajime Yamamoto

Xiaobo Peng

Will Li

Chenhui Ge

Technology for zoned read parameters. The read parameters may include read reference levels and/or offsets applied to base read reference levels. The memory system may assign memory cells located in a region (e.g., block) into zones based on a ranking of a target read level for each set of memory cells in the region. The memory system may assign word lines in a block into zones based on a ranking of a target read voltage and/or target read voltage offset for each word line. The memory system may read each particular set of memory cells (e.g., word line in the block) using a representative read voltage for the zone into which the particular word line is assigned.

Read parameter zoning

An apparatus includes a memory structure including non-volatile memory cells, and a control circuit coupled to the memory cell. The control circuit configured to first read a block of non-volatile memory cells using a first plurality of read levels, determine that the first read fails to successfully read the block of non-volatile memory cells, second read the block of memory cells using a second plurality of read levels different from the first plurality of read levels, determine that the second read successfully reads the block of non-volatile memory cells, estimate that the first read failed because of data retention or read disturb, and erase and re-write data to the block of non-volatile memory cells.

Apparatus and methods for read retry with conditional data refresh

A non-volatile memory is configured to transition memory cells from programmed data states with the higher ranges of threshold voltages to programmed data states with the lower ranges of threshold voltages without the transitioning the memory cells to the erased data state.

Non-volatile memory with decline state operation

A non-volatile memory includes non-volatile memory cells divided into blocks, bit lines connected to the blocks, and a source line connected to the blocks. Each block includes multiple sub-blocks. Each sub-block includes multiple source side Gate Induced Drain Leakage ('GIDL') generation transistors that are closer to the source line than the bit lines. GIDL generation transistors for each sub-block can be controlled separately from GIDL generation transistors for other sub-blocks of the same sub-block so that sub-blocks can be separately and independently erased and/or GIDL can be used to inhibit unselected sub-blocks from bring disturbed during programming.

Non-volatile memory with sub-block programming

In a word line leakage detection process in a NAND or other non-volatile memory device, to determine leaky blocks of a memory device, a reference value for block is determined by comparing the current drawn by the peripheral circuitry of the block with a sequence of comparison current values, corresponding to a range of digital values, while the peripheral circuit is not connected to the block. The current drawn when the peripheral circuitry is connected to the block is then determined, again by comparison with a sequence of comparison values, but of a reduced range of digital values, running from an offset above the reference value to an offset below the reference value. To further reduce test times, the same reference value is used for a group of blocks, such as groups of blocks that share a set of supply lines.

Self-learning built-in self-test (BIST) for leak detection in non-volatile memory

Technology to prevent over-erase in NAND memory. Each bit line involved in erase is connected to multiple NAND strings. Erase verify of each NAND string is performed at a final target level and a level that is somewhat higher than the final target level. Bit lines are placed into three groups based on the erase status of the NAND strings connected to the bit line. The erase voltage applied to the bit lines in the next erase loop depends on the group in which the bit line was placed.

Smart erase inhibit

A non-volatile memory system reduces the number of bits of data per non-volatile memory cell for a block (or other grouping of non-volatile memory cells) in response to a failed memory operation, the block being subjected to more than a minimum number of programming cycles or other events. The reducing of the number of bits of data stored in the memory cells allows the useful life of the block to be extended.

Non-volatile memory that dynamically reduces the number of bits of data stored per memory cell

Embodiments disclosed herein are directed to a memory device, comprising control circuitry configured to: perform a broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for a first string; perform a narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for the first string; and perform the narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for a second string, wherein the broad voltage level range bit error rate estimation scan includes scanning a broader range of voltage levels than the narrow voltage level range bit error rate estimation scan.

Enhanced bit error rate estimation scan process

The disclosure provides a data matching method, and the method includes inputting to-be-matched first data into a pre-trained vector transformation model, to obtain a first vector corresponding to the first data and a binary vector corresponding to the first vector; obtaining a first intermediate vector using an oblivious transfer protocol, and obtaining a first distance intermediate result based on the first intermediate vector and a first predefined algorithm; receiving a second distance intermediate result generated, based on a second vector, a first random vector, and a second predefined algorithm, and sent by a second device; determining a target distance between the first vector and the second vector based on the first vector, the first distance intermediate result, and the second distance intermediate result; and determining whether the first data and second data match based on the target distance and a predefined first distance threshold.

Data matching method, apparatus and system, and device and medium

Technology for determining a test flow for testing memory during a production phase. The following are accessed: a list of test items with a number of candidate test item conditions for each test item, defects (e.g., bad blocks) detected by each test item condition, a list of benchmark defects (e.g., bad blocks), and judgement criteria. The defects (e.g., bad blocks) for the candidate test item conditions may be compared with the benchmark defects (e.g., bad blocks) in view of judgement criteria. Based on the comparison, at least one test item may be eliminated resulting in a set of remaining test items. A production phase test flow having a test item condition for each remaining test item may be generated.

Memory testing flow set up with computational intelligence

In a word line leakage detection process in a NAND or other non-volatile memory device, a stress selected set of word lines have a high stress voltage applied while other parts of an array are biased to a low level. While stressing the memory array, the current drawn by the array is compared to a leakage detection current that increases in amplitude. For example, this can be done by mirroring the array current and comparing this with the current from a current source that increases in response to a digital input value and determining when it exceeds the mirror current, at which point the stress is discontinued. In addition to determining the amount of leakage, this approach results in low leakage word lines receiving less stress, while greater leakage result in greater amounts of stress being applied.

Adaptive word line stress for leak detection in non-volatile memory

Technology is disclosed herein for a dynamic bitscan. The dynamic bitscan may include performing a first bitscan of a first strict subset of memory cells. Then, based on results of the first bitscan, a determination is made whether to perform a second bitscan of a second strict subset of memory cells. Prior to the bitscan(s) a verify reference voltage may be applied to both strict subsets of memory cells. Skipping the second bitscan saves considerable time. However, the second bitscan is performed at least sometimes, which increases accuracy. The first strict subset of memory cells and the second strict subset of memory cells may have different locations relative to some point in the block that contains the memory cells. The first strict subset of memory cells and the second strict subset may have different programming speeds.

Dynamic bitscan for non-volatile memory

Technology is disclosed herein compensating for neighbor memory cell interference on a target memory cell when reading the target memory cell. The voltage that is applied to the bit line associated with the target memory cell may have a magnitude that depends on the data state of the neighbor memory cell. The magnitude of the voltage on the bit line may impact the amount of drain-induced barrier lowering (DIBL) experienced by the target memory cell. The amount of DIBL may be used to provide a desired amount of compensation for the neighbor memory cell interference. A higher bit line voltage may be used to create a greater amount of DIBL and therefore greater amount of compensation for neighbor memory cell interference.

Fast direct look ahead read mode in a memory device

Embodiments of this application provide antenna switching methods and apparatuses. In an implementation, a first communication device determines a first antenna identifier based on air interface transmission information, the first communication device sends the first antenna identifier to a digital switch, and the digital switch switches from a second switch state to a first switch state based on the first antenna identifier, where the first switch state indicates that a second communication device communicates with the first antenna within a first time unit, and the second switch state indicates that the second communication device communicates with a second antenna within a second time unit.

Antenna switching method and related device

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in memory holes. The memory holes are arranged in rows comprising strings which are grouped into blocks comprising a first plane and a second plane. A control means is configured to program memory cells of the first plane and the second plane connected to one of the word lines using iterations of a program operation. The control means terminates programming of the first plane prior to completing programming of the first plane in response to determining the first plane programs slower than the second plane by a predetermined number of the iterations of the program operation. The control means adjusts the predetermined number of the iterations based on an additional verify iteration performed on at least some of the memory cells beyond the iterations of the program operation.

Smart early program termination algorithm for neighbor plane disturb countermeasure

Growing community of inventors

Shanghai, China

Liang Li