Rambus Inc.

Intel Corporation

Tcl Research America Inc.

Liang Leon Peng

Bohuslav Rychlik

Thomas J Sheffler

Lawrence Lai

Steven Spangler

Craig Edward Hampel

Haohong Wang

Steven Cameron Woo

Qi Lin

Yoav Harel

Yimin Yang

Thomas A Sheffler

A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

Command-differentiated storage of internally and externally sourced data

A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Data write from pre-programmed register

DRAM with command-differentiated storage of internally and externally sourced data

Memory component that performs data write from pre-programmed register

Single command, multiple column-operation memory device

For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2&#xd7;2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2&#xd7;2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.

Multi mode texture sampler for flexible filtering of graphical texture data

Multi-mode texture filters suitable for performing both bilinear filtering based on a fractional texture address and generating a weighted average of a group of texel values based on predetermined texel weighting coefficients as dependent on a filter mode signal. In embodiments, the weighted average may be accumulated over a variety of filter footprints. In embodiments, multi-mode texture filter logic includes a plurality of flexible filter blocks. In further embodiments, a pair of flexible filter blocks staged with each performing one lerp phase in the bilinear filter mode while a pair of flexible filter blocks in the flexible filter mode generate a weighted average over a pair of texels of a texel quad. In embodiments, each flexible filter block has a same microarchitecture, enabling an efficient utilization in either bilinear filter or flexible filter mode.

Flexible filter logic for multi-mode filtering of graphical texture data

Land grid array socket for electro-optical modules

Texture filter logic suitable for determining a minimum or maximum texel value from a plurality of texel values associated with a filter footprint of arbitrary shape and size. In embodiments, logic circuitry includes a plurality of min/max comparison block stages is configured to perform comparisons and determine a min/max value of predetermined number of texel groups. In embodiments, the logic circuitry further includes a number of min/max collectors to accommodate filter footprints having more texel groups than the predetermined number accommodated by the min/max comparison block stages. Iterative comparisons may be performed until all texel groups in the given footprint have been compared. In further embodiments, the logic circuitry outputs four min/max texel values, which may then be further processed with a final comparison stages to arrive at one min/max value for a footprint.

Minimum-maximum filtering of graphical texture data

An automatic face annotation method is provided. The method includes dividing an input video into different sets of frames, extracting temporal and spatial information by employing camera take and shot boundary detection algorithms on the different sets of frames, and collecting weakly labeled data by crawling weakly labeled face images from social networks. The method also includes applying face detection together with an iterative refinement clustering algorithm to remove noise of the collected weakly labeled data, generating a labeled database containing refined labeled images, finding and labeling exact frames containing one or more face images in the input video matching any of the refined labeled images based on the labeled database, labeling remaining unlabeled face tracks in the input video by a semi-supervised learning algorithm to annotate the face images in the input video, and outputting the input video containing the annotated face images.

Automatic face annotation method and system

An object identification method is provided. The method includes dividing an input video into a number of video shots, each containing one or more video frames. The method also includes detecting target-class object occurrences and related-class object occurrences in each video shot. Further, the method includes generating hint information including a small subset of frames representing the input video and performing object tracking and recognition based on the hint information. The method also includes fusing tracking and recognition results and outputting labeled objects based on the combined tracking and recognition results.

Object identification system and method

A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

Growing community of inventors

San Jose, CA, United States of America

Liang Leon Peng