Apple Inc.

University of Texas System

Molecular Imprints, Inc.

Globalfoundries Inc.

Toyota Motor Engineering & Manufacturing North America, Inc.

Toyota Jidosha Kabushiki Kaisha

Liang Kai Wang

Andrew M Havlir

Dzung Q Vu

Sidlgata V Sreenivasan

Byung-Jin Choi

Frank Y Xu

Michael R Bruce

Gerard M Schmid

Michael Nevin Miller

Hongfei Jia

Shuqiang Yang

Mohamed M Hilali

Fen Wan

Hisao Kato

Joan F Brennecke

Oscar Morales Collazo

Mahadevan Ganapathisubramanian

Yeong-Jun Choi

Alex Ruiz

A dimeric ionic liquid that enhances and improves the performance and durability of a fuel cell catalyst. The dimeric ionic liquid comprises 1,1-(butane-1, 4-diyl)bis(9-methyl-3,4,6,7,8,9-hexahydro-2H-pyrimido[1,2-a]pyrimidin-1-ium 1,1,2,2,3,3,4,4,4-nonafluorobutane-1-sulfonate. Membrane electrode assemblies (MEAs) and polymer electrolyte membrane fuel cells (PEMFCs) employing the dimeric ionic liquid are also disclosed.

Ionic liquid to enhance performance and durability of membrane assembly electrode (MEA)

A protonated dimeric ionic liquid that enhances and improves the performance of a fuel cell catalyst. The protonated dimeric ionic liquid comprises 9'9&#x2032;-(butane-1,4-diyl)bis(3,4,6,7,8,9-hexahydro-2H-pyrimido[1,2-a]pyrimidin-1-ium) 1,1,2,2,3,3,4,4,4-nonafluorobutane-1-sulfonate. Membrane electrode assemblies (MEAs) and polymer electrolyte membrane fuel cells (PEMFCs) employing the protonated dimeric ionic liquid are also disclosed.

Protonated dimeric ionic liquid to enhance performance of membrane assembly electrode (MEA)

Techniques are disclosed relating to low-level instruction storage in a processing unit. In some embodiments, a graphics unit includes execution circuitry, decode circuitry, hazard circuitry, and caching circuitry. In some embodiments the execution circuitry is configured to execute clauses of graphics instructions. In some embodiments, the decode circuitry is configured to receive graphics instructions and a clause identifier for each received graphics instruction and to decode the received graphics instructions. In some embodiments, the caching circuitry includes a plurality of entries each configured to store a set of decoded instructions in the same clause. A given clause may be fetched and executed multiple times, e.g., for different SIMD groups, while stored in the caching circuitry.

Instruction storage

Techniques are disclosed relating to low-level instruction storage in a graphics unit. In some embodiments, a graphics unit includes execution circuitry, decode circuitry, hazard circuitry, and caching circuitry. In some embodiments the execution circuitry is configured to execute clauses of graphics instructions. In some embodiments, the decode circuitry is configured to receive graphics instructions and a clause identifier for each received graphics instruction and to decode the received graphics instructions. In some embodiments, the hazard circuitry is configured to generate hazard information that specifies dependencies between ones of the decoded graphics instructions in the same clause. In some embodiments, the caching circuitry includes a plurality of entries each configured to store a set of decoded instructions in the same clause and hazard information generated by the decode circuitry for the clause. This may reduce power consumption, in some embodiments, by reducing hazard checking when clauses are executed multiple times.

GPU instruction storage

Systems and methods for fabrication of nanostructured solar cells having arrays of nanostructures are described, including nanostructured solar cells having a repeating pattern of pyramid nanostructures, providing for low cost thin-film solar cells with improved PCE.

Nanostructured solar cell

Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway.

Semiconductor chip with backside conductor structure

Energy sources and methods for curing in an imprint lithography system are described. The energy sources may include one or more energy elements positioned outside of the viewing range of an imaging unit monitoring elements of the imprint lithography system. Each energy source is configured to provide energy along a path to solidify polymerizable material on a substrate.

Energy sources for curing in an imprint lithography system

A loading unit, surface scanning module, and an imprint module may be integrated into a single tool. Template may be loaded on loading unit and positioned within imprint module. Substrate may then be loaded on loading unit and scanned defects using surface scanning module. If substrate passes inspection by surface scanning module, substrate may be positioned imprint module where formable material may be dispensed thereon and imprinted. The imprinted substrate may then be unloaded from imprinting module.

Imprint lithography system and method

Growing community of inventors

Austin, TX, United States of America

Liang Kai Wang