Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Liang-Hung Chen

Yen-Chung Chen

Wen-Juh Kang

Jung-Chi Huang

Shih-Chi Wu

Meng-Chin Tsai

A clock and data recovery (CDR) circuit and method are disclosed herein. The CDR circuit includes a data analysis module, a loop filter module and a phase adjust module. The data analysis module generates an error signal according to an input data, a first clock signal, and a second clock signal. The loop filter module generates a first corrective signal according to the error signal, a frequency threshold value, and a phase threshold value. The phase adjust module generates the first clock signal and the second clock signal according to the first corrective signal. The loop filter module further accumulates the error signal to generate an accumulated value, and to compare the accumulated value with an accumulated threshold value, so as to dynamically adjust the accumulated threshold value, the frequency threshold value, and the phase threshold value.

Clock and data recovery circuit and method

An eye diagram measuring circuit includes a reference signal generator, a clock data recovery circuit, a test signal generator, and a boundary determining unit. The reference signal generator generates a reference signal. The clock data recovery circuit generates a clock signal according to the reference signal. The test signal generator generates a first sampling signal according to the clock signal. The test signal generator discriminates logic levels of plural bits of the input signal according to the first sampling signal and a slicing voltage, thereby generating a test signal. The boundary determining unit generates a boundary of an eye diagram according to a relationship between the test signal and the reference signal. The test signal generator changes a phase of the first sampling signal and a magnitude of the slicing voltage according to plural conditions provided by the boundary determining unit.

Eye diagram measuring circuit and measuring method thereof

Eye diagram scan circuit and associated method for a receiver circuit, including a level adjust circuit, a phase interpolator and a control module. The receiver circuit provides a first data signal and a primary phase data according to a received signal. The control module provides a phase offset data and a level offset data. The level adjust circuit adjusts a level of the received signal in respond to the level offset data; the phase interpolator triggers according to a sum of the phase offset data and the primary phase data, so a second data signal is provide in response to the level-adjusted received signal. The control module compares the first data signal and the second data signal, and accordingly provides an eye diagram scan result for the phase offset data and the level offset data.

Eye diagram scan circuit and associated method

A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.

Growing community of inventors

Hsinchu, Taiwan

Liang-Hung Chen