Qualcomm Incorporated

Liang Han

Yun Du

Lin Chen

Andrew Evan Gruber

Chun Yu

Guofang Jiao

Alexei Vladimirovich Bourd

Chihong Zhang

Eric Demers

Xiangdong Jin

Zilin Ying

Jing Wu

Hongjiang Shang

Techniques are described to perform a shuffle operation. Rather than using an all-lane to all-lane cross bar, a shuffler circuit having a smaller cross bar is described. The shuffler circuit performs the shuffle operation piecewise by reordering data received from processing lanes and outputting the reordered data.

Shuffler circuit for lane shuffle in SIMD architecture

Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.

General purpose register allocation in streaming processor

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San Diego, CA, United States of America

Liang Han