Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Basf Se Corporation

Autodesk, Inc.

Liang Han

Liang Chen

Shengfen Chiu

Hai Ying Wang

Horst Binder

Harald Schaefer

Tong Zhang

Sheng Fen Chiu

Jing He

Garrick D Evans

Harald Schäfer

Carolyn E Kreisel

Shintaro Gomyo

Woosuk Lee

A memory structure is provided in the present disclosure. The memory structure includes a substrate, a plurality of discrete memory gate structures on the substrate where each of the plurality of memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer, an isolation layer formed between adjacent memory gate structures where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, an opening is formed on an exposed sidewall of the control gate layer, and a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and a metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

Memory structure and fabrication method thereof

A method for manufacturing a flash memory device is provided. The method includes: providing a substrate structure including a substrate, a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, and a gap structure between the gate structures; forming an overhang surrounding an upper portion of the gate structures to form a gap structure between the gate structures; and forming a second isolation region filling an upper portion of the gap structures and leaving a first air gap between the gap structures.

Method for manufacturing semiconductor memory having reduced interference between bit lines and word lines

A memory structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of discrete memory gate structures on the substrate where an isolation trench is between adjacent memory gate structures and a memory gate structure includes a floating gate layer and a control gate layer, forming an isolation layer in the isolation trench where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, forming an opening on an exposed sidewall of the control gate layer where a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

A flash memory device includes a substrate, a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, a gap structure between the gate structures, and a second isolation region filling an upper portion of the gap structure and leaving a first air gap in a lower portion of the gap structure.

Semiconductor memory having reduced interference between bit lines and word lines

A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. Each first gate structure includes a floating gate structure and a control gate structure. The control gate structure includes a body region and a top region. A size of the top region is smaller than a size of the body region along a direction perpendicular to a length direction of the control gate structure. A sidewall of the top region is connected to a sidewall of the body region. The method also includes forming a dielectric layer on the base substrate and covering the plurality of first gate structures, while simultaneously forming air gaps in the dielectric layer between the adjacent first gate structures. A top of each air gap is above or coplanar with a top surface of the control gate structure.

Memory and fabrication method thereof

The present invention relates to a new process for preparing polyisocyanates containing isocyanurate groups and being flocculation-stable in solvents from (cyclo)aliphatic diisocyanates.

Process for preparing polyisocyanates which are flocculation-stable in solvents from (cyclo)aliphatic diisocyanates

A method, apparatus, and article of manufacture provide the ability to edit in-place a ZIP&#x2122; archive file. A file and a first file block (FFB) in a first block location are opened and modified. If the first block location can accommodate the modified FFB, the modified FFB is saved, in-place, in the first block location without rewriting the entire archive. However, if the first block location cannot accommodate the modified FFB, a second file block is copied from a second block location to a third block location located at an end of a file data section of the archive. A portion of the second block location is marked as a free block and the modified FFB is saved without rewriting the entire ZIP&#x2122; archive. The archive is then saved by updating and saving both the central directory and end of central directory.

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Shanghai, China

Liang Han