Micron Technology Incorporated

International Business Machines Corporation

Autoliv Development Ab

Liang Ge

Chen Hui Xu

Liang Chen

Bo Yu

Xia Li

Adrian Stephen Butter

Jie Wang

Xiao Feng Tang

Suo Ming Pu

Licheng Yu

Jia Lian Tang

Gong Qiong Li

Weijing Liu

Suoming Pu

Methods, systems, and devices for a dynamic interval for entering a low power state are described. A memory system or device may support a low power mode, which the memory system or device may enter in response to a command from a host system. In some cases, an amount of idle time observed by the host system before issuing such a command may vary based on a status of maintenance operations for the memory system or device. Additionally or alternatively, after receiving such a command, the memory system or device may complete one or more pending maintenance operations before entering the low power mode.

Dynamic interval for a memory device to enter a low power state

Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.

Light hibernation mode for memory

Methods, systems, and devices for performance tuning for a memory device are described. In some examples, a memory system may receive a command (e.g., a read command or a write command) that includes an indicator. The indicator may instruct the memory system to suppress one or more portions of the command. For example, the command may be received by an interface of the memory system and the controller may instruct the memory system to suppress one or more operations performed by a processor of the memory system, a storage controller of the memory system, or both. Upon suppressing one or more operations associated with the command, the memory system may output a response to the test system, which may allow for the test system to tune one or more performance aspects of the memory system.

Performance tuning for a memory device

Methods, systems, and devices for alignment of activation periods are described. Techniques for memory operations are described. A device may transition from a reduced-power state to a reception-ready state based on a timing parameter of the device that indicates a first duration for transitioning the device from the reduced-power state to the reception-ready state. After transitioning to the reception-ready state, a data transmission may be received beginning at a first time. A second time associated with an error in the data transmission may be determined. The timing parameter may be configured to indicate a second duration for transitioning the device to the reception-ready state based on a difference between the second time and the first time.

Alignment of activation periods

An engagement and disengagement device used in a seat belt retractor including a first rotating member capable of being driven to rotate about a rotation axis thereof, a second rotating member provided coaxially with the first rotating member and connected to a reel of the seat belt retractor in an anti-torsion manner, and a transmission member provided between the first and second rotating member. The first rotating member is capable of transmitting torque to the second rotating member by means of the transmission member. The transmission member includes a holder and a transmission element in the holder. A first elastic component elastically holds the transmission element by radially exerting a force that enables the transmission element to be located away from the first or the second rotating member, and the first elastic component is integrated on the holder.

Clutch device

Methods, systems, and devices for cache allocation techniques are described. The memory system may receive a write command that includes a stream identification (ID) associated with performance constraints for data streams. The memory system may determine an application identification (ID) that indicates a type of data based on the stream ID of the write command. In some cases, the memory system may assign a level associated with the application ID that indicates an amount of data to be written for the write operation and allocate an amount of space available to be written for the write operation in a single-level cell cache based on the assigned level. The memory system may write the data to the single-level cell cache within the amount of space of the single-level cell cache.

Cache allocation techniques

An engagement and disengagement device used in a seat belt retractor includes a first rotating member and a second rotating member configured to be coaxial, and a transmission member disposed between the first and second rotating members. The first rotating member defines an engagement portion on a radial inner surface thereof, and the distance from the engagement portion to an axis of rotation gradually increases in a first direction of rotation. The transmission member can rotate between an engagement position and a non-engagement position relative to the first rotating member.

Engaging and disengaging device, seat belt retractor, and seat belt assembly

The present invention discloses a method and system for clock tree planning for an ASIC, the method comprising: determining a netlist and a timing constraint file of the ASIC; creating a sequential device undirected graph for sequential devices in the netlist according to connection relationships of the sequential devices in the netlist and timing constraint relationships of the sequential devices in the timing constraint file; grouping the sequential devices in the netlist according to the sequential device undirected graph, such that the sequential devices in one group do not have a timing constraint relationship with the sequential devices in another group. The ASIC design method improved by using this method will reduce the design cycle from weeks to days, and enable designer to quickly plan the clock tree, thus reducing the design time and improving the design efficiency.

Clock tree planning for an ASIC

Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections is determined based, at least in part, on the target timing path associated with the first of the plurality of sub-connections. The timing probability value indicates a probability that timing closure is satisfied on the target timing path. The route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion. A current connection constraint associated with the first of the plurality of sub-connections is modified in accordance with a connection constraint model to which the first of the plurality of sub-connections corresponds.

Constraint optimization of sub-net level routing in asic design

Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.

Method for estimating the latency time of a clock tree in an ASIC design

A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.

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Shanghai, China

Liang Ge