Inphi Corporation

Marvell Asia Pte., Ltd.

Nec Corporation

Liang Ding

Radhakrishnan L Nagarajan

Roberto Coccioli

Mark Patterson

Steve Aboagye

Junichi Fujikata

Jun Ushida

Shiyang Zhu

Ming-Bin Yu

An optical communication system includes a co-packaged optical module and a heatsink mounted to the co-packaged optical module. The co-packaged optical module includes a processor disposed on a substrate and a plurality of light engines disposed at different locations around the processor on the substrate. The processor and the light engines generating different amounts of heat during operation. The heatsink includes a plurality of heat pipes non-uniformly distributed throughout the heatsink to remove the different amounts of heat generated at a location of the processor and respective locations of the different ones of the light engines.

Heatsink for co-packaged optical switch rack package

An in-packaged multi-channel light engine is packaged for four or more sub-assemblies of optical-electrical sub-modules. Each is assembled with at least four laser chips, one or more driver chip, and one or more trans-impedance amplifier (TIA) chip separately flip-mounted on a silicon photonics interposer and is coupled to an optical interface block and an electrical interface block on a sub-module substrate. The in-packaged multi-channel light engine further includes a first frame fixture holding the four or more sub-assemblies and a second frame fixture configured to hold the first frame fixture with the four or more sub-assemblies. The in-packaged multi-channel light engine further includes an interposer plate inserted between the sub-module substrates and a module substrate and is compressed between a backplate member attached to a bottom side of the module substrate and a top plate member configured as a heatsink with a plurality of fin structures.

In-packaged multi-channel light engine on single substrate

A co-packaged optical module includes a substrate, a processor arranged on the substrate and a plurality of light engines mounted around the processor on the substrate using mounting assemblies configured to attach the respective light engines to the substrate. The light engines and the mounting assemblies are disposed along a perimeter of the substrate, including at corners of the substrate. Each of the mounting assemblies includes a socket, a metal clamp clamping a corresponding one of the light engines into the socket, and a plurality of pins which when mated with corresponding holes in the substrate cause peripheries of the mounting assemblies, including the light engines, the sockets and the metal clamps, to be flush with the perimeter of the substrate.

Method for co-packaging light engine chiplets on switch substrate

A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.

Light engine based on silicon photonics TSV interposer

A co-packaged optical-electrical module includes a module substrate with a minimum lateral dimension no greater than 100 mm. The co-packaged optical-electrical module further includes a main die with a processor chip disposed at a central region of the module substrate, the processor chip being configured to operate with a digital-signal processing (DSP) interface for extra-short-reach data interconnect. Additionally, the co-packaged optical-electrical module includes a plurality of chiplet dies disposed densely along a peripheral region of the module substrate. Each chiplet die is configured to be self-packaged light engine on a sub-module substrate with a minimum lateral dimension to allow a maximum number of chiplet dies on the module substrate with a distance of any chiplet die from the main die smaller than 50 mm for extra-short-reach interconnect operation.

Co-packaged light engine chiplets on switch substrate

A method for co-packaging multiple light engines in a switch module is provided. The method includes providing a module substrate with a minimum lateral dimension no greater than 110 mm. The module substrate is configured with a first mounting site at a center region and a plurality of second mounting sites distributed densely along the peripheral sides. The method includes disposing a main die with a switch processor chip at the first mounting site. The switch processor chip is configured to operate with a digital-signal processing (DSP) interface for extra-short-reach data interconnect. The method further includes mounting a plurality of chiplet dies respectively into the plurality of second mounting sites. Each chiplet die is configured to be a packaged light engine with a minimum lateral dimension to allow a maximum number of chiplet dies with &#x3c;50 mm from the main die for extra-short-reach data interconnect.

An integrated heatsink for a co-packaged optical-electrical module includes a base plate attached on top of a co-packaged optical-electrical module. The integrated heatsink further includes a plurality of fin structures extended upward from the base plate except a central cavity region with missing sections of fins, each fin extended along an axial direction from a front edge to a back edge of the base plate except some trenches shallow in depth across some fin structures and some other trenches deep in depth down to the base plate either along or across some fin structures. Additionally, the integrated heatsink includes multiple heat pipes including shaped portions embedded in the trenches in the plurality of fin structures. At least one bottom horizontal portion per heat pipe is brazed to the base plate in a corresponding region that is superimposed on hot spots of the co-packaged optical-electrical module under the base plate.

A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.

Compact optical module integrated for communicating cryptocurrency transaction

An optical transceiver by hybrid multichip integration. The optical transceiver includes a PCB with a plurality of prefabricated surface bonding sites. A first chip includes a FOWLP package of multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer is disposed on the PCB by respectively bonding a plurality of conductor balls between the dielectric redistribution layer and the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) in the dielectric molding layer. The optical transceiver further includes a second chip configured as a Sipho die comprising photonics devices embedded in a SOI wafer substantially free from any electronics device process. The second chip is stacked over the first chip with multiple conductor bumps being bonded respectively to the soldering material in the multiple TMVs.

Optical transceiver by FOWLP and DOP multichip integration

An silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiOoverlying the first plurality of Si waveguides and a second plurality of SiNwaveguides formed on the first layer of SiO. At least one SiNwaveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiOwith a thickness controlled no greater than 90 nm. The device includes a second layer of SiOoverlying the second plurality of SiNwaveguides. The method of accurately controlling the coupling interlayer SiOthickness includes a multilayer SiO/SiN/SiOhard mask process for SiOetching and polishing as stopping and buffering layer as well as Si waveguide etching mask.

Growing community of inventors

Singapore, Singapore

Liang Ding