Apple Inc.

Liang Deng

Norman Jay Rohrer

Yizhang Yang

Arpit Mittal

Rohit Kumar Gupta

John H Kelm

Assaf Menachem

Ido Y Soffair

Oren Kerem

Meir Harar

Prabhu Rajamani

Manu Gulati

Sukalpa Biswas

Robert E Jeter

Rakesh L Notani

Gregory S Mathews

Kai Lun Hsiung

Fabien S Faure

Venkata Ramana Malladi

Enming Zheng

Michael L Liu

Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

Backlight reconstruction and compensation-based throttling

In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

Dynamic refresh rate control

Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

Systems and methods for dynamically switching memory performance states

Techniques are disclosed relating to asymmetric circuits. In some embodiments, a storage element is configured to maintain a first input value as an input to an asymmetric circuit during a time interval. For example, in one embodiment, the time interval may correspond to a frame of video data and the storage element may be configured to store a filter coefficient for the frame of video data. In some embodiments, the storage element may be configured to store the value as a constant for multiple operations by the asymmetric circuit. In some embodiments, the asymmetric circuit is configured to generate a plurality of output values based on the first input value and respective ones of a set of second input values. In some embodiments, the asymmetric circuit is leakage power asymmetric and/or critical path asymmetric. This may increase performance and/or reduce power consumption.

Asymmetric circuitry

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Saratoga, CA, United States of America

Liang Deng