Qualcomm Incorporated

Prominent Communications, Inc.

Liang Dai

Dinesh Jagannath Alladi

Omid Rajaee

Masoud Roham

Li-chung Chang

Lennart Karl-Axel Mathe

Prasad Srinivasa Siva Gudem

Kentaro Yamamoto

Ganesh Kiran

Changsok Han

Jeffrey Todd Bridges

Lennart Karl Mathe

Xiaohong Quan

Song Shi

Behnam Sedighi

Kevin Hsi-Huai Wang

Seyed Arash Mirhaj

Yu Song

Lam Van Nguyen

Yuhua Guo

Wei Zheng

Mohammad Meysam Zargham

Li Lu

Weihua Chen

Brandon Wayne Lewis

Jie Huang

Hung-Chuan Pai

Bruce Lee

Chandra Satya Priyanka Tirupathi

Li-Chung Chang

Song S Shi

A device includes a first plurality of MEOL interconnects coupled to a second node that extends in a first direction. The first plurality of MEOL interconnects includes first and second subsets of MEOL second-terminal interconnects. The device includes a second plurality of MEOL interconnects coupled to a first node that extends in the first direction. The second plurality of MEOL interconnects includes first and second subsets of MEOL first-terminal interconnects. The first subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a first subset of interleaved MEOL interconnects. The second subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a second subset of interleaved MEOL interconnects. The device includes at least one of a first plurality of gate interconnects or a first plurality of OD regions extending in a second direction orthogonal to the first direction between the first and second subsets of interleaved MEOL interconnects.

High density linear capacitor in semiconductor technologies

A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV) coupled to the first inverter (INV), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV) coupled to the second inverter (INV), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

Analog-to-digital converter, phase sampler, time-to-digital converter, and flip-flop

An apparatus includes a first plurality of low noise amplifiers (LNAs) and a cascaded switch configured to route outputs of the first plurality of LNAs to a second plurality of LNAs.

Cascaded switch between pluralities of LNAS

Certain aspects of the present disclosure provide apparatus and techniques for analog-to-digital conversion using a time-to-digital converter (TDC). For example, certain aspects provide a quantizer using a TDC. The quantizer may include at least one first capacitive element and a set of switches configured to selectively couple a first terminal and a second terminal of the at least one first capacitive element to at least one input voltage source. The TDC may also include a reference voltage source, at least one switch coupled between the second terminal of the at least one first capacitive element and an output of the reference voltage source, a current source selectively coupled to the first terminal of the at least one first capacitive element, and a voltage sense circuit coupled to the first terminal of the at least one first capacitive element.

Time-to-digital converter (TDC)-based quantizer

Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror, which may be used for distributed sensing of a remote current in an integrated circuit (IC). One example current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. An input node between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low-voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.

Low voltage, highly accurate current mirror

Exemplary embodiments are related to voltage regulators. A device may include a first energy storage element coupled between a ground voltage and an output. The device may also include a second energy storage element coupled to the ground voltage and configured to selectively couple to the output. Further, the device may include a voltage regulator coupled between an input and the second energy storage element.

Charge sharing linear voltage regulator

Certain aspects of the present disclosure provide methods and apparatus (e.g., a level shifter) for buffering an oscillating signal generated by an oscillator. One example apparatus generally includes an amplifier having a first amplification stage configured to amplify the oscillating signal generated by the oscillator and a second amplification stage configured to amplify an inverse of the oscillating signal generated by the oscillator; and a sensing circuit configured to adjust an operational bandwidth of the amplifier based on a frequency of the oscillating signal.

Wide frequency/voltage-ratio buffer with adaptive power consumption

Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

Segmented successive approximation register (SAR) analog-to-digital converter (ADC) with reduced conversion time

Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer

An analog-to-digital converter includes: a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; a noise shaping module configured to compare the first input signal to the second input signal received, and to output a digital output signal and a residue signal in a first phase of a noise shaping operation; and a storage module configured to store the residue signal during the first phase of the noise shaping operation, the storage module configured to receive an analog input signal and remove the residue signal from the analog input signal in a second phase of the noise shaping operation to output a new first input signal to the noise shaping module.

Noise shaping successive approximation register analog-to-digital converter

A push-pull driver is provided with a differential amplifier that amplifies a difference between an input voltage and an output voltage to drive a bias node coupled to a diode-connected bias transistor. The push-pull driver is configured to control the drain-to-source voltage for a source-follower output transistor having its gate tied to a gate for the diode-connected bias transistor to be proportional to the drain-to-source voltage for the diode-connected bias transistor. This proportionality prevents excessive static current variation that would otherwise be present in the source-follower output transistor.

Push-pull voltage driver with low static current variation

Techniques for performing noise cancellation/attenuation are disclosed. In one design, an apparatus includes a power supply generator having a switcher, a coupling circuit, an envelope amplifier, and a feedback circuit. The switcher generates DC and low frequency components and the envelope amplifier generates high frequency components of a supply voltage for a load, e.g., a power amplifier. The switcher receives a first supply voltage and provides a switcher output signal having switcher noise. The coupling circuit receives the switcher output signal and provides a first output signal having a first version of the switcher noise. The feedback circuit receives the switcher output signal and provides a feedback signal. The envelope amplifier receives an envelope signal and the feedback signal and provides a second output signal having a second version of the switcher noise, which is used to attenuate the first version of the switcher noise at the load.

Power supply generator with noise cancellation

Techniques for creating one or more notch frequencies in the power density spectrum of an output voltage generated by switching circuitry. In an aspect, high- and low-side switches are coupled to an output voltage via an inductor. The spectral power of the output voltage at one or more frequencies is estimated, and the estimated spectral power is provided to a switch controller controlling the switches. The switch controller may be configured to switch the switches only in response to detecting that the estimated spectral power at the notch frequency is at a minimum. In certain exemplary aspects, the techniques may be incorporated in an envelope-tracking system, wherein the switching circuitry forms part of a switched-mode power supply (SMPS) supplying low-frequency power to a power amplifier load.

Noise shaping for switching circuitry

A low distortion feed forward delta sigma modulator includes a first adder configured to receive a feedback signal and an input signal. The modulator also includes a first integrator configured to receive an output from the first adder, and a second integrator configured to receive an output from the first integrator. The modulator further includes a second adder configured to receive a second integrated path from the second integrator, a first integrating path from the first integrator and a first summing path from the input signal. The modulator also has a last integrator configured to receive an output from the second adder.

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San Diego, CA, United States of America

Liang Dai