Mosel Vitelic Corporation

Mosel Viltelic, Inc.

Liang-Choo Hsia

Thomas Chang

Thomas Tong-Long Chang

Der-Tsyr Fan

Jr-Min Tsaur

The present invention provides an improved method for forming metalization layers for inter-layer connections including the steps of first providing a substrate, then depositing a metal layer on the substrate, then depositing a dielectric layer overlying the metal layer, etching away an opening in the dielectric layer to expose at least partially the metal layer, and etching an opening in the metal layer by using the dielectric layer as a mask to at least partially expose the underlying substrate. The method may optionally includes the step of blanket depositing a thin oxide layer and then an inter-level dielectric layer on top of the device.

Method for forming metalization for inter-layer connections

A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Inverse-T tungsten gate apparatus

An antireflection coating (116) for use in fabricating integrated circuits and electronic devices comprises a film of chromium oxide, CrO, or chromium suboxide, CrO.sub.x where x&lt;1. An antireflection layer reduces the standing waves and topographic notching in a photoresist layer (118) when applied over a highly reflective layer (114). Highly reflective layers may be metals, such as aluminum or gold, silicides, or semiconductors, such as silicon. These coatings are preferably made by reactive sputtering of a chromium target with a partial pressure of oxygen in the sputtering chamber. The antireflection layer works primarily by absorptive, rather than wave matching, principles. This antireflection layer exhibits good adhesion and may be integrated into the device. Integrating the layer into the device may reduce stress in the underlying layers and improve device yields and reliability.

Circuit structure with an anti-reflective layer

A method of forming a capacitor that has improved charge storage capacity in a high density memory device that has shallow trench isolation regions and a capacitor produced by the method are provided. The method includes the step of forming an oxide spacer that consists of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again decoratively etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with an increased surface area leading to an improved charge storage capacity.

Stacked capacitor having improved charge storage capacity

A method of forming a LDD fabrication by automatic phosphoric silicate glass (PSG) doping is disclosed herein. A phosphoric silicate glass serves as a diffusion source. The phosphorous ions of phosphoric silicate glass can be driven into a substrate to form a lightly-doped drain (LDD)by a high temperature during a thermal annealing process. The diffusion method can prevent from the damage in the substrate and the increasing of leakage current. Additionally, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from sequentially diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can effectively control the impurity concentration of the lightly-doped drain (LDD) to prevent from the impurity concentration of the LDD over high.

Method of forming lightly-doped drain by automatic PSG doping

A method of fabricating single-side corrugated cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. The corrugated capacitor shape is achieved by depositing the thermal chemical vapor deposition (CVD) oxide and the plasma-enhanced CVD (PECVD) oxide alternating layers. Then, the thermal CVD oxide and the PECVD oxide layers are lateral etched by hydrofluoric acid (HF). Because hydrofluoric acid (HF) etches the thermal CVD oxide at a slower rate than etches the PECVD oxide, a cavity (undercut) is formed in each PECVD oxide layer. Therefore, the single-side corrugated shape capacitor surface is created that increases the surface area of the capacitor considerably. The cylindrical capacitor storage node of the DRAM capacitor of this method has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices.

Single-side corrugated cylindrical capacitor structure of high density

Method of making an inverse-T tungsten gate

A method of forming a capacitor that has improved charge storage capability and a capacitor produced by such method are provided. The method utilizes an additional layer of oxide spacer consisting of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with a substantially increased surface area leading to an improved charge storage capability.

Method of forming stacked capacitor having corrugated side-wall structure

A method of fabricating double-side corrugated cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. The corrugated capacitor shape is achieved by depositing the thermal chemical vapor deposition (CVD) oxide and the plasma-enhanced CVD (PECVD) oxide alternating layers. Then, the thermal CVD oxide and the PECVD oxide layers are vertically etched to form two trenches followed by laterally etched by hydrofluoric acid (HF). Because hydrofluoric acid (HF) etches the thermal CVD oxide at a slower rate than etches the PECVD oxide, a cavity is formed in each PECVD oxide layer along the trenches. Finally, polysilicon layer is deposited filling into the trenches. Therefore, the double-side corrugated shape capacitor surface is created that increases the surface area of the capacitor considerably. The cylindrical capacitor storage node of the DRAM capacitor of this method has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices.

Double-side corrugated cylindrical capacitor structure of high density

A method of forming a cell contact that has improved structural strength and break-down resistance and a cell contact produced by such method are provided. The method utilizes an oxide spacer consisting of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a straight contact opening is first etched by a plasma etching technique, the hole is again etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a contact opening having a corrugated side-wall is formed and into which a polysilicon is deposited to substantially fill the hole. A cell contact having a corrugated side-wall configuration is thus formed which presents improved structural rigidity and break-down resistance. A layer of rugged polysilicon layer may optionally be deposited before the deposition of the polysilicon into the contact opening to further increase the surface area of the cell contact.

Method of making corrugated cell contact

The present invention provides a wafer metrology pattern integrating both overlay and critical dimension features for SEM or AFM measurements. The present invention provides an improved test mask target which contains lines measuring 0.25 .mu.m, 0.3 .mu.m, and 0.5 .mu.m. The spaces between the lines can be adjusted accordingly. The improved test mask target provides a pattern that combines the wafer critical dimension and box-in-box overlay targets into a single structure. As a result, the pattern may be used for both overlay and critical dimension verifications in a single AMF or SEM measurement. More precisely, wafer overlay and critical dimension disposition may be made simultaneously, reducing the need to perform multiple measurements at each testing step.

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Taipei, Taiwan

Liang-Choo Hsia