Yangtze Memory Technologies Co., Ltd.

Wuhan University

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Huazhong University of Science and Technology

Changjiang River Scientific Research Institute, Changjiang Water Resources Commission

Liang Chen

Wei Liu

Yanhong Wang

Zhiliang Xia

Wenxi Zhou

Kun Zhang

Cheng Gan

Yuancheng Yang

Lei Xue

Shi Qi Huang

Wenshan Xu

Shao-Fu Sanford Chu

Ruizhi Chen

Xin Wu

Yanwei Shi

Shiqi Huang

Ning Jiang

Chao Sun

Shunfu Chen

Wu Tian

Lei Wang

Zhen Li

Jian Zhang

Yan Wang

Xin Zhou

Jing Feng

Deren Li

Jiangang Jiang

Chunxia Zhao

Shulun Liu

Zaiqin Wang

Lin Wang

Huaquan Yang

Zhaoliang Liu

Wei Han

Chengjing Xiao

Jiangtao Yan

Lei Lei

Tao Wei

Yang Bai

Xiaomei Shao

Mei Hu

Hesong Zeng

Lingmin Liao

Da Zhang

Xiaohu Yan

Jingbin Liu

Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first periphery structure. The first array structure includes a first memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The first periphery structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second periphery structure. The second array structure includes a second memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second periphery structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

Three-dimensional memory devices having semiconductor assemblies bonded by bonding layer and methods for forming the same

In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a second trench isolation in the substrate and surrounding a portion of the substrate, and a first routing electrode layer extending through the first trench isolation. The portion of the substrate is an active region of a transistor.

Semiconductor devices, systems, and methods for forming the same

A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an etch stop structure in a first wafer, forming a first through contact in contact with the etch stop structure, bonding the first wafer to a second wafer to electrically connect the first through contact to a CMOS device of the second wafer, and forming a through substrate contact penetrating a first substrate of the first wafer and the etch stop structure, and in electrically contact with the CMOS device through the first through contact.

Three-dimensional memory devices and fabricating methods thereof

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

Structure and method for forming capacitors for a three-dimensional NAND

A three-dimensional (3D) memory device includes a plurality of memory stacks arranged along a first direction, and a dummy block structure disposed between two adjacent memory stacks. Each memory stack includes a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction. A channel structure extends through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction. A first isolation structure is disposed between the dummy block structure and one of the plurality of memory stacks. A substrate is disposed under the plurality of memory stacks, the dummy block structure, and the first isolation structure. A second isolation structure is disposed in the substrate extending along the second direction.

Three-dimensional memory device and method for forming the same

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.

Three-dimensional memory devices and methods for forming the same

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

A semiconductor device includes a semiconductor substrate, a doped region formed in the semiconductor substrate, a source/drain formed in the doped region, a conductive pad formed on the source/drain, a gate dielectric layer disposed over the semiconductor substrate and the doped region exposing the conductive pad, a gate formed on the gate dielectric layer, an insulation layer formed over the gate, the gate dielectric layer, and the conductive pad, and a contact formed in the insulation layer in electric contact with the conductive pad.

Semiconductor device and method for forming the same

The present invention provides a multifunctional pacemaker wire conversion device and an application method thereof. The device includes a box body, a permanent electrode female connector, a permanent electrode male connector, a temporary electrode female connector, a temporary electrode male connector, and a circuit line. A cavity is formed in the box body, the permanent electrode female connector, the permanent electrode male connector, the temporary electrode female connector, and the temporary electrode male connector are disposed on the box body, and the permanent electrode female connector, the permanent electrode male connector, the temporary electrode female connector, and the temporary electrode male connector are electrically connected to each other through the circuit line disposed in the cavity.

Multifunctional pacemaker wire conversion device and application method thereof

In certain aspects, a three-dimensional (3D) memory device includes a single crystalline silicon layer, a polysilicon layer, a transistor in contact with the single crystalline silicon layer, and a channel structure in contact with the polysilicon layer. The polysilicon layer and the single crystalline silicon layer are nonoverlapping and at least partially noncoplanar.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

A method and system for fingerprint positioning based on 5G multi-beam downlink signals, includes: extracting multi-beam SSB from 5G downlink signals, and obtaining multi-beam SSS signal and DM-RS signal from multi-beam SSB; calculating multi-beam reference signal received power RSRP based on multi-beam SSS signal and DM-RS signal; calculating the RSSI of 5G downlink synchronization channel based on multi-beam SSB autocorrelation, and calculating the multi-beam reference signal received quality RSRQ based on multi-beam RSRP and RSSI; stacking the multi-beam RSRP and RSRQ to form multi-beam fingerprint features; inputting multi-beam fingerprint characteristic into neural networks, and the neural networks output positioning results.

Method and system for fingerprint positioning based on 5G multi-beam downlink signals

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

Peripheral circuit having recess gate transistors and method for forming the same

In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of bit lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Memory peripheral circuit having three-dimensional transistors and method for forming the same

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A transistor is formed in a first region on a first side of a single crystalline silicon substrate. A step layer is formed in a second region on the first side of the single crystalline silicon substrate. A channel structure extending through a stack structure and in contact with the step layer is formed. The stack structure includes interleaved dielectric layers and conductive layers on the step layer. Part of the single crystalline silicon substrate that is in the second region is removed from a second side opposite to the first side of the single crystalline silicon substrate to expose the step layer from the second side.

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Wuhan, China

Liang Chen