Analog Devices,inc.

Liam Joseph White

Brian Anthony Moane

David J Clarke

Denis Ellis

Michael G Tuthill

Michael P Daly

Kieran K Heffernan

John Twomey

Denis J Doyle

Colm Patrick Ronan

Keith A Moloney

An output stage interface circuit for interfacing with a data bus, comprising first and second rails for receiving respectively a high voltage and a low voltage from a power supply; a data output terminal; a first main switch element coupled between said terminal and the first rail and comprising a first main MOS device having a gate and an independently configurable back gate, and responsive to a first data control signal applied to the gate pulling the voltage on the data output terminal toward the first rail voltage; and a first control circuit responsive to the voltage on said terminal being pulled from a first state across a first voltage reference to a second state for coupling said back gate to said terminal and permitting coupling of the gate of said MOS device to said terminal, the first main MOS device presenting a high impedance on the terminal when its voltage is pulled to the second state.

Output stage interface circuit for outputting digital data onto a data bus, and a method for operating an output stage interface circuit

An output stage interface circuit () comprises a main bipolar transistor (Q) coupling a data output terminal () to a first rail () to which the positive of the power supply voltage (V) is applied, and a substrate diffusion isolated main NMOS transistor (MN) coupling the data output terminal () to a second rail () which is held at ground. Control signals from a data control circuit () selectively operate the main bipolar transistor (Q) and the main MOS transistor (MN) for determining the logic high and low states of the data output terminal () during data output. A back gate () of the main MOS transistor (MN) is independently configurable, and is selectively and alternately coupleable to one of the second rail () and the data output terminal () in response to the voltage on the data output terminal (), so that when the voltage on the data output terminal () is pulled below a voltage reference (V), the back gate () is coupled to the data output terminal () for preventing a parasitic bipolar transistor (Q) and a parasitic diode (D) of the main MOS transistor (MN) sourcing current to the data bus. First and second primary buffer circuits () and () are coupled between the first rail () and the back gate () of the main MOS transistor (MN), so that when the voltage on the data output terminal () is pulled below the voltage reference (V), the base () and the gate () of the main bipolar transistor (Q) and the main MOS transistor (MN) can be pulled to the voltage on the data output terminal () for maintaining the main bipolar transistor (Q) and the main MOS transistor (MN) in the off-state.

Output stage interface circuit for outputting digital data onto a data bus

An input protection device is provided for protecting a circuit structure which is coupled to a first node, the device comprising a first lightly-doped region of P-type material with a lightly doped well of N-type material formed in it. Two regions of heavily doped N-type and P-type material, which are electrically connected to the first node, are formed in the well of N-type material. A third heavily doped region of N type material is formed in the first lightly-doped region of P-type material and is electrically connected to a reference node. In a first aspect of this invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this first aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node. In a second aspect to the invention, a further region of heavily doped P-type material is formed in the first lightly-doped region of P-type material. In a third aspect to the invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this third aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node, with a further region of heavily doped P-type material formed in the first lightly-doped region of P-type material. Accordingly, an input protection device for protecting pins of an integrated circuit is described having both bipolar and unipolar characteristics. The input protection device may be constructed as a discrete device or as part of an integrated circuit and provides for breakdown voltages in excess of a supply voltage to an integrated circuit. The characteristics, in particular the breakdown voltage, of the input protection device are alterable by adjusting its layout, in contrast to a known method of altering such characteristics by altering doping levels.

SCR cell for electrical overstress protection of electronic circuits

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County Limerick, Ireland

Liam Joseph White