International Business Machines Corporation

Krusin-elbaum, Lia

Newns, Dennis M.

Lia Krusin-Elbaum

Dennis Merton Newns

Bruce Gordon Elmegreen

Kuan-Neng Chen

Chung H Lam

Matthew R Wordeman

Xiao Hu Liu

Sampath Purushothaman

Michael John Brady

Albert M Young

Glenn John Martyna

Deok-Kee Kim

Mohamed O Aboelfotoh

Chandrasekharan Kothandaraman

Richard Joseph Gambino

Robert L Sandstrom

James Patrick Doyle

Byeongju Park

Christy Sensenich Tyberg

Yuan-Chen Sun

Lawrence Alfred Clevenger

Subramanian Srikanteswara Iyer

Praveen Chaudhari

Xinlin Wang

Robert B Laibowitz

Simone Raoux

Roger Hilsen Koch

James F Ziegler

George A Sai-Halasz

Padmanabhan Santhanam

Ralph R Ruf

Rudolf Ludeke

Eti Ganin

Martin Muser

Tsuyoshi Tamegai

William T Masselink

Kuang-Neng Chen

James Russell Thompson, Jr

Paul William Lisowski

Alan David Marwick

Takasada Shibauchi

A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

High density low power nanowire phase change material memory device

A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal.

Three-terminal cascade switch for controlling static power consumption in integrated circuits

A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

A coupling structure for coupling piezoelectric material generated stresses to an actuated device of an integrated circuit includes a rigid stiffener structure formed around a piezoelectric (PE) material and the actuated device, the actuated device comprising a piezoresistive (PR) material that has an electrical resistance dependent upon an applied pressure thereto; and a soft buffer structure formed around the PE material and PR material, the buffer structure disposed between the PE and PR materials and the stiffener structure, wherein the stiffener structure clamps both the PE and PR materials to a substrate over which the PE and PR materials are formed, and wherein the soft buffer structure permits the PE material freedom to move relative to the PR material, thereby coupling stress generated by an applied voltage to the PE material to the PR material so as change the electrical resistance of the PR material.

Coupling piezoelectric material generated stresses to devices formed in integrated circuits

Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.

Programmable via devices in back end of line level

A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode and a third electrode, wherein the first electrode comprises a gate terminal, the second electrode comprises a common terminal, and the third electrode comprises an output terminal such that an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material.

Piezo-effect transistor device and applications

Reconfigurable devices and methods for the fabrication thereof are provided. In one aspect, a reconfigurable device is provided. The reconfigurable device comprises a substrate; a first dielectric layer on the substrate; a conductive layer recessed into at least a portion of a side of the first dielectric layer opposite the substrate; at least one second dielectric layer over the side of the first dielectric layer opposite the substrate, so as to cover the conductive layer; a heater within the second dielectric layer; at least one programmable via extending through the second dielectric layer, extending through and surrounded by the heater and in contact with the conductive layer, the programmable via comprising at least one phase change material; a capping layer over the programmable via; a first conductive via and a second conductive via, each extending through the second dielectric layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive layer.

Four-terminal reconfigurable devices

Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device includes a first dielectric layer; a heater over the first dielectric layer; an air gap separating at least a portion of the heater from the first dielectric layer; an isolation layer over the first dielectric layer covering at least a portion of the heater; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via including at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.

Programmable via devices with air gap isolation

A method of fabricating a programmable via structure is provided. The method includes providing a patterned heating material on a surface of an oxide layer. The oxide layer is located above a semiconductor substrate. A patterned dielectric material is formed having a least one via on a surface of the patterned heating material. The at least one via is filled with a phase change material such that a lower surface of the phase change material is in direct contact with a portion of the patterned heating material. A patterned diffusion barrier is formed on an exposed surface of the at least one via filled with the phase change material. A method of programmable a programmable via structure made by the method is also disclosed.

Programmable via structure and method of fabricating same

A piezoelectrically programmed, non-volatile memory cell structure includes a programmable piezo-resistive hysteretic material (PRHM) that is capable of being interconverted between a low resistance state and high resistance state through applied pressure cycling thereto; a piezoelectric material mechanically coupled to the PRHM such that an applied voltage across the piezoelectric material results in one of a tensile or compressive stress applied to the PRHM, depending upon the polarity of the applied voltage; and one or more electrodes in electrical communication with the PRHM, wherein the one or more electrodes are configured to provide a write programming current path through the piezoelectric material and a read current path through the PRHM.

Piezo-driven non-volatile memory cell with hysteretic resistance

Growing community of inventors

Dobbs Ferry, NY, United States of America

Lia Krusin-Elbaum