Taiwan Semiconductor Manufacturing Comp. Ltd.

Li-Zhen Yu

Cheng-Chi Chuang

Chih-Hao Wang

Lin-Yu Huang

Huan-Chieh Su

Chia-Hao Chang

Yu-Ming Lin

Kuan-Lun Cheng

Chun-Yuan Chen

Shih-Chuan Chiu

Lo-Heng Chang

Jia-Chuan You

Tien-Lu Lin

Pei-Yu Wang

Yi-Hsun Chiu

Sheng-Tsung Wang

Ching-Wei Tsai

Zhi-Chang Lin

Shang-Wen Chang

Kuan-lun Cheng

Yen-Ming Chen

Chung-Liang Cheng

Dian-Hau Chen

Chien-Hao Chen

Hsiang-Ku Shen

Yu-Xuan Huang

Chih-Tang Peng

Jr-Hung Li

Chi-On Chui

De-Wei Yu

Ying-Liang Chuang

Shih-Wei Wang

Bo-Cyuan Lu

Tsung-Chieh Hsiao

Hung-Yi Huang

Min-Hsiu Hung

Yen-Chun Huang

Cheng-Po Chau

Chia-Lin Chuang

Jin-Mu Yin

Chun-Cheng Chou

Huang-Lin Chao

Pinyen Lin

An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Integrated circuit structure with backside via rail

A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.

Semiconductor device with air gaps and method of fabrication thereof

A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Dual side contact structures for source/drain regions in semiconductor transistor devices and method of forming

A method of fabricating a semiconductor device includes providing a dummy structure including channel layers disposed over a frontside of a substrate, inner spacers disposed between adjacent channels of the channel layers and at lateral ends of the channel layers, and a gate structure interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. Perform an etching process to etch the gate structure and the plurality of channel layers to form a cut region along the active edge. Deposit a conductive material in the cut region to form a conductive feature. The method further includes thinning the substrate from a backside of the substrate to expose the conductive feature and forming a backside metal wiring layer on the backside of the substrate. The backside metal wiring layer is in electrical connection with the conductive feature.

Semiconductor device with backside power rail

A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.

Integrated circuit structure with backside interconnection structure having air gap

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

Spacers for semiconductor devices including backside power rails

A semiconductor device includes a plurality of stacks that each includes a plurality of nanostructures stacked over each other, a gate structure wrapping around the nanostructures and extending between the stacks, source and drain structures, and a plurality of fin structures respectively disposed on the stacks. A first surface of the gate structure between the stacks is substantially coplanar with first surfaces of the fin structures facing to the nanostructures or between the first surfaces of the fin structures and the nanostructures.

Fins disposed on stacks of nanostructures where the nanostructures are wrapped around by a gate

A method is provided for forming a contact plug by bottom-up metal growth. In one step, a substrate is etched to form a contact hole that exposes a silicon-containing feature in the substrate. In one step, a silicide layer is formed on the silicon-containing feature. In one step, a metal seed layer is formed over the silicide layer. In one step, a metal contact layer is deposited over the metal seed layer to form the contact plug in the contact hole.

Method for forming a contact plug by bottom-up metal growth

Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

Semiconductor device having backside via and method of fabricating thereof

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

Semiconductor device structure and methods of forming the same

A method includes forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip; forming a gate structure over the semiconductor layers; etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure; forming epitaxial layers in the recesses, respectively; forming isolation layers over the epitaxial layers, respectively; forming epitaxial source/drain structures over the isolation layers, respectively; performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layer, and one of the isolation layer, wherein one of the epitaxial source/drain structures is exposed through the via opening; and forming a backside via in the via opening.

Semiconductor transistor device includes backside via electrically connecting epitaxial source/drain structures and method for forming the same

A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Method for forming long channel back-side power rail device

A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Semiconductor devices with backside power rail and method thereof

A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

Semiconductor device having dielectric hybrid fin

A semiconductor device structure includes a source/drain (S/D) feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a first silicide layer in contact with the first surface of the S/D feature, a second silicide layer opposing the first silicide layer and in contact with the second surface of the S/D feature, a front side S/D contact in contact with the first silicide layer, a back side S/D contact in contact with the second silicide layer, a semiconductor channel layer comprising a sidewall in contact with the sidewall of the source/drain feature, a gate dielectric layer surrounding exposed surfaces of the semiconductor layer, an interlayer dielectric (ILD) disposed adjacent to the gate dielectric layer, and a liner disposed between and in contact with the ILD and the gate dielectric layer.

Growing community of inventors

Taipei, Taiwan

Li-Zhen Yu