United Microelectronics Corp.

Li-Yeat Chen

Wen-Yi Hsieh

Hsiao-Ling Lu

Haber Chen

Wen-Yi Shieh

This invention provides a method of forming a self-aligned silicide of a semiconductor wafer, the surface of the semiconductor wafer comprising at least one silicon device. A cobalt-containing metallic layer is formed on the semiconductor wafer which covers on the surface of the silicon device. A first thermal treatment process is performed to rapidly heat the semiconductor wafer up to 300&tilde;500&deg; C. for 10&tilde;50 seconds and form Co,Si on the surface of the silicon device. A second thermal treatment process is performed to rapidly heat the semiconductor wafer up to 400&tilde;680&deg; C. for 20&tilde;50 seconds and then cool down the semiconductor wafer afterwards so as to convert Co,Si into CoSi. An etching process is performed to remove the metallic layer. A third thermal treatment process is performed to rapidly heat the semiconductor wafer up to 700&tilde;950&deg; C. for 30&tilde;60 seconds and then cool down the semiconductor wafer afterward so as to convert CoSi into the self-aligned silicide.

Method of forming a self-aligned silicide on a semiconductor wafer

Several processes for forming semiconductor gate structures having treated titanium silicide layers are disclosed. There are at least three methods been provided for the present invention and a summarized general procedure of all the methods comprises the following steps: The first step is to provide a silicon substrate having a gate oxide layer formed on top the silicon substrate, and forming a polysilicon layer over the gate oxide layer, followed by the formation of a TiN layer over the polysilicon layer. A treated titanium silicide layer is then formed on top of the TiN layer. Sequentially, an anti-reflection (SiON) film is deposited on top of the treated titanium silicide layer with a capping layer formed over the anti-reflection film. Finally, patterning and etching the above layers to expose a portion of the gate oxide layer and to form a gate electrode, where the final gate structure is rounded up by a rapid thermal process (RTP). The step of forming a treated titanium silicide layer further comprises one of the following: impurity doping by implantation, sputtering with nitrogen gas, and using TiSi.sub.x M.sub.y target. As a result of this, a wider thermal-stress window has been achieved by the present invention.

Growing community of inventors

Hsin-Chu, Taiwan

Li-Yeat Chen