Vanguard International Semiconductor Corporation

Li Yeat Chen

Ing-Ruey Liaw

Sen-Huan Huang

DRAM cells having zigzag-shaped stacked capacitors with hemispherical gain (HSG) surfaces to increase capacitance is achieved. FET gate electrodes are formed having a planar first insulating layer thereon. Contact openings are etched for bit line contacts and capacitor node contacts. A first polysilicon layer having a top silicide layer is patterned to form bit lines and node contacts. A planar second insulating layer is formed with openings to the node contacts, which are filled with a second polysilicon to form electrical connections. A etch-stop layer is deposited followed by a multilayer composed of alternating layers of phosphosilicate and borosilicate glass. Recesses are etched in the multilayer to the node contacts, and the sidewalls in the recesses are isotropically etched to form a zigzag profile. A doped amorphous silicon layer is deposited and treated to form a HSG layer. An insulating layer is formed in the recesses to provide an etch mask and the HSG layer is etched back. The multilayer and the insulating layer are removed to provide zigzag-shaped/HSG capacitor bottom electrodes. An interelectrode dielectric layer is deposited, and a patterned fourth polysilicon layer is used to form the top electrodes to complete the array of capacitors.

Method for making dynamic random access memory (DRAM) cells having

An array of DRAM cells having brush-shaped stacked capacitors with increased capacitance is achieved. A first planar insulating layer is formed having openings over the FET source/drain areas for node contacts. A doped first polysilicon layer and a silicide layer are deposited and patterned to form bit lines and concurrently form the capacitor node contacts in the openings. A planar second insulating layer is deposited with second openings aligned over the node contacts. A multilayer composed of a doped second polysilicon layer, an etch end-stop layer (silicide or undoped polysilicon), a thick doped third polysilicon layer, and a thin insulating layer is deposited and patterned to form the capacitor bottom electrodes. A thin hemispherical-shaped grain (HSG) fourth polysilicon layer is deposited and used as an etch mask to form a sieve-like mask in the third insulating layer on the top of the bottom electrode. The sieve-like mask is then used to anisotropicaly etch the bottom electrode to the etch-stop layer without overetch to form a brush-like electrode while retaining the HSG layer on the sidewalls of the bottom electrodes to increase capacitor area. An interelectrode dielectric layer and a doped fifth polysilicon layer are deposited and patterned to complete the improved stacked capacitors for the DRAM devices.

Method for making dynamic random access memory cells having brush-shaped

A method for making DRAM cells with minimum active device areas (cell areas) using novel sidewall-spacer bit lines is achieved. A trench is etched in an insulating layer aligned over the device areas and orthogonal to the gate electrodes, and extending over the first and second source/drain areas. A conducting layer is deposited and etched back to form sidewall-spacer bit lines. A planar second insulating layer is formed in which bit line contact openings are etched between the sidewall-spacer bit lines to the first source/drain areas. The contact openings are filled with a third conducting layer to form the bit line contacts. A third insulating layer is deposited and capacitor node contact openings are etched between the sidewall-spacer bit lines and to the second source/drain areas. An insulating layer is deposited and etched back to insulate the sidewall-spacer bit lines in the node contact openings and a fourth con-ducting layer is deposited and etched back to form the node contacts. By this self-aligned method, the minimum unit cell area (device area) can be reduced to about 6F.sup.2, where F is the minimum feature size for the current technology. Any one of the current stacked capacitor structures, such as crown, fin-shaped, and the Like, can now be built on the node contacts to provide memory cells with increased packing density.

Dynamic random access memory (DRAM) cells with minimum active cell areas

A crown capacitor for a memory device is formed using (1) an important early poly plug 42 process and (2) an etch barrier layer 34. A first insulating layer 30 and an etch barrier layer are formed over device structures and the substrate 10. A node contact hole 40 is formed through the etch barrier layer 34 and the first insulating layer 30. A plug 42 is formed filling the node contact hole 40. Next, a planarizing layer 44 is formed over the etch barrier layer 34 and the plug 42. A crown hole 46 is formed in the planarizing layer 44 exposing the plug 42. A first polysilicon layer 50 is deposited over the etch barrier layer, the plug 42, and the remaining first planarizing layer 44A. A Sacrificial layer 54 is formed over the first polysilicon layer 50 thereby filling the crown hole 46. The sacrificial layer 54 and the first polysilicon layer 50 are etch back to remove the exposed portions of the first polysilicon layer 50 over the planarizing layer 44A. The sacrificial layer 54 is selectively removed thereby forming a crown shaped storage electrode 42 50.

Method for crown type capacitor in dynamic random access memory

A method of forming a capacitor having a cross section shape similar to the Greek letter psi. The shape of the capacitor plate provides a high capacitance using a modest amount of chip area. A capacitor hole is etched in a thick layer of a first dielectric. A layer of polysilicon is formed on the dielectric layer covering the sidewalls and bottom of the capacitor hole. A second dielectric is then used to fill the hole. A contact hole in the second dielectric extends to the contact region of the wafer and is filled with a polysilicon plug. The polysilicon plug and the polysilicon covering the sidewalls and bottom of the capacitor hole form the first capacitor plate. A layer of hemispherical grain polysilicon can be used to further increase the surface area of the first capacitor plate.

Method of making greek letter psi shaped capacitor for DRAM circuits

A method for making DRAM cells with minimum active device areas (cell areas) using novel sidewall-spacer bit lines is achieved. A trench is etched in an insulating layer aligned over the device areas and orthogonal to the gate electrodes, and extending over the first and second source/drain areas. A conducting layer is deposited and etched back to form sidewall-spacer bit lines. A planar second insulating layer is formed in which bit line contact openings are etched between the sidewall-spacer bit lines to the first source/drain areas. The contact openings are filled with a third conducting layer to form the bit line contacts. A third insulating layer is deposited and capacitor node contact openings are etched between the sidewall-spacer bit lines and to the second source/drain areas. An insulating layer is deposited and etched back to insulate the sidewall-spacer bit lines in the node contact openings and a fourth con-ducting layer is deposited and etched back to form the node contacts. By this self-aligned method, the minimum unit cell area (device area) can be reduced to about 6F.sup.2, where F is the minimum feature size for the current technology. Any one of the current stacked capacitor structures, such as crown, fin-shaped, and the like, can now be built on the node contacts to provide memory cells with increased packing density.

Growing community of inventors

Hsinchu, Taiwan

Li Yeat Chen