Tsinghua University

Li-Yang Hong

Meng-Fan Chang

Ping-Chun Wu

Jin-Sheng Ren

Jian-Wei Su

Ho-Yu Chen

A dynamic differential-reference time-to-digital converter for computing-in-memory applications is controlled by a bias reference and a predetermined setting parameter, and includes a configurable main-reference selector and a plurality of time-to-digital converters. The configurable main-reference selector is configured to receive a plurality of edge-output signals, select one of the edge-output signals as a main reference and select others of the edge-output signals as a plurality of edge selected signals according to the predetermined setting parameter. One of the time-to-digital converters is configured to compare the bias reference with the main reference to output a bias multiplication-and-accumulation value, and others of the time-to-digital converters are configured to compare the main reference with the edge selected signals to output a plurality of differential multiplication-and-accumulation values. The bias multiplication-and-accumulation value and the differential multiplication-and-accumulation values are dynamically adjusted according to the bias reference and the predetermined setting parameter.

Memory array structure with dynamic differential-reference based readout scheme for computing-in-memory applications, dynamic differential-reference time-to-digital converter for computing-in-memory applications and computing method thereof

A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Growing community of inventors

Hsinchu, Taiwan

Li-Yang Hong