United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Powerchip Technology Corporation

Li-Wei Liu

Li-Wei Feng

Chien-Ting Ho

Ying-Chiao Wang

Wen-Chieh Lu

Hung-Lin Shih

Le-Tien Jung

Yi-Chung Liang

Chen-Hao Huang

Hsuan-Tung Chu

Shih-Kuei Yen

Hann-Ping Hwang

Guan-Yi Liou

Huai-Jin Hsing

Ming-Che Li

A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.

DRAM and flash structure and method of fabricating the same

A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

Semiconductor memory device

Semiconductor memory device and manufacturing method thereof

A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced.

Static random access memory and manufacturing method thereof

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Kaohsiung, Taiwan

Li-Wei Liu