Taiwan Semiconductor Manufacturing Comp. Ltd.

M31 Technology Corporation

National Yang Ming Chiao Tung University

Giantplus Technology Co., Ltd

Flytech Technology Co., Ltd.

Li-Wei Chu

Jam-Wem Lee

Wun-Jie Lin

Yu-Ti Su

Chih-Wei Chang

Po-Lin Peng

Ming-Fu Tsai

Ming-Hsing Tsai

Hung-Hsu Chen

Chun-Yu Lin

Nan-Chun Lien

Ying-Chi Su

Han-Jen Yang

Yu-Kai Chen

Bo-Ting Chen

Wei-Yip Loh

Yu-Hsiang Liao

Ching-Hwanq Su

Yi-Feng Chang

Chia-Jung Chang

Hung-Yi Huang

Ya-Huei Li

Jen-Chou Tseng

Po-Tsun Liu

Chia-Wei Hsu

Chun-Wen Nieh

Hsiang-Hui Cheng

Tao Yi Hung

Shu-Yu Su

Ming-Dou Ker

Chun-Hsien Huang

Yu-Hung Lin

Wei-Jung Lin

Ming-Hsiang Song

Sheng-Hsuan Lin

Ming Hsien Tsai

Tzu-Heng Chang

Chia-Hui Chen

Ming-Hsien Tsai

Hung-Chang Hsu

Yu-Shiuan Wang

Ping-Fang Hung

Guang-Ting Zheng

Ku-Huang Lai

Ting-Wei Chang

Yi-Chun Kuo

Chun-Yen Chen

Chih-wei Chang

Min-Hsiu Hung

Tse-Hua Lu

Ching-Te Chuang

Yu-Ying Hsu

Ming-Fang Lai

Wei-Chiang Shih

Chen-Wei Lin

Yi-Hsiang Chao

Ming-Hsien Tu

Kan-Ju Lin

Che-Yao Wu

Kai-Ju Chou

Li-Chun Chou

Kuan-Yu Yeh

Chi-Hung Chuang

Chao-Kuei Chung

Wei-Nan Liao

Chi-Shin Chang

Po-Chun Huang

Wei-Min Wu

Tsun-Lai Hsu

Shih-Hsuan Lin

Yu-Wei Yeh

Shiang-Yu Tsai

Chew-Pu Jou

Jian-Jia Wang

Shou Ming Liu

Yuh-Jiun Lin

The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit to discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Semiconductor device and electrostatic discharge clamp circuit

A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node. The clamp circuit further includes a first transistor of a first type. The first transistor has a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. The clamp circuit further includes a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node.

Electrostatic discharge (ESD) protection circuit and method of operating the same

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes an epitaxial structure and a metal silicide layer. The epitaxial structure includes a semiconductor material. The metal silicide layer is disposed on the epitaxial structure. The metal silicide layer includes the semiconductor material, a first metal material and a second metal material. An atomic size of the first metal material is greater than an atomic size of the second metal material, and a concentration of the first metal material in the metal silicide layer varies along a thickness direction.

Semiconductor structure and manufacturing method thereof

A method for manufacturing a semiconductor structure includes: forming a patterned structure which includes a first semiconductor portion and a second semiconductor portion, the first and second semiconductor portions having different materials; and performing an oxide formation process to oxidize the first and second semiconductor portions such that a first oxidation layer formed on the first semiconductor portion has a thickness less than that of a second oxidation layer formed on the second semiconductor portion.

Method for forming dual silicide in manufacturing process of semiconductor structure

Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.

ESD power clamp devices and circuits

A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Electrostatic discharge diodes with different sizes and methods of manufacturing thereof

An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Ammonium fluoride pre-clean protection

Semiconductor device pre-cleaning

A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.

Circuit module with reliable margin configuration

In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Circuit and method for high voltage tolerant ESD protection

A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.

Method of making semiconductor device electrostatic discharge diode

A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.

Circuit module with improved line load

A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

Device and method for operating the same

An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.

Planar and non-planar FET-based electrostatic discharge protection devices

A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

Semiconductor device having multiple electrostatic discharge (ESD) paths

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Hsinchu, Taiwan

Li-Wei Chu