United Microelectronics Corp.

Agency for Science, Technology and Research

Micron Technology Incorporated

Marvell International Limited

Li Wang

Purakh Raj Verma

Ching-Yang Wen

Kai Cheng

Hem P Takiar

Hong Wan Ng

Motoichi Kurisawa

Joo Eun Chung

Enyong Tai

Fan Lee

Guchang Han

Bo Tao

Dong Yin

Jian Xie

Yi Yan Yang

Zhibiao Zhou

Zhimin Yuan

Bo Liu

Siang Huei Leong

Chenchen Jacob Wang

Chun Lian Ong

Weiya Xi

Khai Leong Yong

Jianzhong Shi

Kui Cai

Chao Bi

Zhi Yong Ching

Quan Jiang

Pantelis Sophoclis Alexopoulos

Kheong Sann Chan

Qide Zhang

Jing Zhang

Budi Santoso

Moulay Rachid Elidrissi

Zhimin He

Runshun Wang

Chiew Leong Wong

Jiang Feng Hu

Tiejun Zhou

Mengjun Liu

Wuzhong Lin

Sufui Sophia Tan

Yansheng Ma

Leonard Gonzaga

Wee Kiat Lim

Ke Gan

Phyu Hla Nu

Wei Hua

Cheng Su Soh

Shengkai Yu

Yin Quan Yu

Kannan Sundaravadivelu

Ningyu Liu

Jianqiang Mou

Boon Long Ibrahim See

Venkataramanan Venkatakrishnan

Keming Xu

Hirohisa Yano

Jinjun Qiu

Cheng Peng Tan

Wee Kay Yeo

Chong Wee Lee

Gang Ren

A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

Overlapping die stacks for NAND package architecture

A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.

Method of fabricating an air gap

A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

Semiconductor structure

Overlapping die stacks for nand package architecture

A method of fabricating a semiconductor device is provided. First, a semiconductor structure is provided, and the semiconductor structure includes a buried dielectric layer, a first gate structure disposed on a front-side of the buried dielectric layer, and a first source/drain region and a second source/drain region disposed between the buried dielectric layer and the first gate structure. Then, a trench is formed in the buried dielectric layer. Afterwards, a conductive layer is formed on the buried dielectric layer and in the trench. Finally, the conductive layer is patterned.

Semiconductor device and method of fabricating the same

A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a trench, and a contact layer. The first gate structure is disposed on a front-side of the buried dielectric layer, and the second gate structure is disposed on a backside of the buried dielectric layer. The first source/drain region and a second source/drain region are disposed between the first gate structure and the second gate structure. The trench is formed in the buried dielectric layer, and the contact layer is disposed in the trench and electrically coupled to the second source/drain region, where the contact structure and the second gate structure are formed of the same material.

A semiconductor device assembly includes a substrate having a plurality of external connections, a first stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

A semiconductor device comprises a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a front-side metallization, a backside metallization, and conductive contacts. The first gate structure and the second gate structure disposed respectively in the front-side and back side of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structures. The front-side metallization is disposed on the front-side of the buried dielectric layer, and the backside metallization is disposed on the backside of the buried dielectric layer. The conductive contacts penetrate the buried dielectric layer and electrically couple the front-side metallization to the backside metallization.

A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.

Semiconductor device

A composite is disclosed. The composite comprises a first conjugate of a polymer and a first phenol-containing moiety, and a second conjugate of a gelatin or collagen and a second phenol-containing moiety, wherein the polymer is selected so that the first conjugate is less cell-adhesive than the second conjugate, at least one of the first and second conjugates is crosslinked to form a matrix, and the composite comprises discrete regions that are rich in one of said first and second conjugates. A method of forming such composite is also disclosed. The method comprises mixing precursors for the first and second conjugates in a solution for forming said composite, and dispersing a catalyst in the solution to catalyze crosslinking of at least one of the first and second conjugates to form the matrix. The composite may be used to grow cells.

Phase separated composite

According to an embodiment of the present invention, a data storage device comprising a motor having a stator is disclosed. The stator may include a substrate having a first surface and a second surface opposite to the first surface; and a n-phase winding arrangement having n phase windings; wherein each phase winding comprises m flat fractional-pitch coils arranged on the first surface of the substrate such that the coils are spaced apart uniformly along a closed loop and connected in series; wherein each coil together with an angular section of the substrate between the coil and an adjacent coil of the same phase winding defines a stator pole-pair; and wherein m is an integer larger than 1.

Data storage device

In a process of forming a hydrogel from a mixture comprising hydrogen peroxide (HO), horseradish peroxidase (HRP), and a polymer comprising a crosslinkable phenol group, the gelation rate in the solution and the crosslinking density in the hydrogel can be independently adjusted or controlled by selection of the molarity of HOand concentration of HRP in the solution when the molarity of HOis limited to be within a range and the concentration of HRP is limited to be above a threshold. A method for determining the range and threshold is disclosed. The hydrogel may be used to grow cells, in which case, the molarity of HOmay be selected to affect the differentiation or growth rate of the cells in the hydrogel. Also, the hydrogel system may be used for sustained delivery of a therapeutic protein, for example in the treatment of liver cancer, fibrosis or hepatitis.

Formation of hydrogel in the presence of peroxidase and low concentration of hydrogen peroxide

An ultrahigh differential current perpendicular to the plane dual spin valve read head with high pinning stability. The high pinning stability may be achieved using the same anti-ferromagnetic materials for two spin valves by introducing a double synthetic anti-ferromagnetic structure in one of the two spin valves.

Sensor arrangement

A process for preparing a thermosensitive polymer from a microemulsion is provided. The microemulsion comprises a monomer capable of forming a thermosensitive polymer and a polymerizable surfactant. Additional comonomers may be included in the microemulsion to vary the properties of the polymers produced. The resulting thermosensitive polymers may be nanoporous. The polymers according to the invention are suitable for use in medical applications, including use as a wound dressing and for delivery of cells to a graft site.

Thermosensitive polymers for therapeutic use and methods of preparation

In a process of forming a hydrogel from a mixture comprising hydrogen peroxide (HO), horseradish peroxidase (HRP), and a polymer comprising a crosslinkable phenol group, the gelation rate in the solution and the crosslinking density in the hydrogel can be independently adjusted or controlled by selection of the molarity of HOand concentration of HRP in the solution when the molarity of HOis limited to be within a range and the concentration of HRP is limited to be above a threshold. A method for determining the range and threshold is disclosed. The hydrogel may be used to grow cells, in which case, the molarity of HOmay be selected to affect the differentiation or growth rate of the cells in the hydrogel.

Growing community of inventors

Singapore, Singapore

Li Wang