Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Taiwan Semiconducor Manufacturing Company, Ltd.

Li-Te S Lin

Pinyen Lin

Han-Yu Lin

Tze-Chung Lin

Fang-Wei Lee

Chao-Hsien Huang

Jung-Hao Chang

Po-Chin Chang

Ru-Gun Liu

Wei-Liang Lin

Yu-Tien Shen

Yi-Chen Lo

Chansyun David Yang

Ya-Wen Yeh

Yung-Sung Yen

Wei-Hao Wu

Ya Hui Chang

Yi-Ruei Jhan

Kuo-Cheng Ching

Yuan-Hung Chiu

Li-Chih Chao

Yi-Lun Chen

Fo-Ju Lin

Yu-Lien Huang

Hun-Jan Tao

Shih-Chun Huang

Wei-Lun Chen

Kuan-Da Huang

Chan-Syun David Yang

Chun-Hsiung Lin

Tsang-Jiuh Wu

Chun-Feng Nieh

Ming-Huan Tsai

Yi-Shan Chen

Chun-Jui Huang

Shu-Hao Kuo

Chin-Hsiang Lin

Tze-Liang Lee

Ming-Ching Chang

Kuei-Shun Chen

Tzer-Min Shen

Chin-Yuan Tseng

Akira Mineji

Wei-Yen Woon

Gwan-Sin Chang

Chiu-Hsiang Chen

Chan Syun David Yang

Yu-Ming Lin

Keng-Chu Lin

Huan-Just Lin

Chan-Lon Yang

Chung-Cheng Wu

Shi-Ning Ju

Min Cao

Nai-Han Cheng

Chi-Chun Chen

Fu-Ting Yen

Wen-Ting Lan

Ching-Yi Chen

Hui OuYang

Yen-Tien Tung

Kuo-An Liu

Christine Y Ouyang

Chien Wen Lai

Keh-Chiang Ku

Kenichi Sano

Jhih-Rong Huang

Chih-Chien Chang

Zhi-Qiang Wu

Bharath Kumar Pulicherla

Hsun Chang

Chung-Ru Yang

Hao-Heng Liu

Gary Chan

Chia-Shiung Tsai

Chih-Ming Lai

Shi Ning Ju

Ryan Chia-Jen Chen

Ming-Hua Yu

Pang-Yen Tsai

Shiang-Bau Wang

Cheng-Ming Lin

Hua-Tai Lin

Yi-Nien Su

Chen-Nan Yeh

Hsien-Hsin Lin

Jian-Hong Chen

Yu-Rung Hsu

Chien-Wen Lai

Fang-Cheng Chen

Chih-Ching Wang

Jiing-Feng Yang

Chun-Yu Chen

Chin-Chiu Hsia

Tzu-Li Lee

Li-Shiun Chen

Szu-Hua Chen

Bang-Chien Ho

Chih-Long Chiang

The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

High selectivity etching with germanium-containing gases

The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.

Method for fabricating a semiconductor device including etching nanostructures

A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.

Isolation structure for semiconductor device

The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

Dry etching of semiconductor structures with fluorine-containing gases

A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.

Semiconductor arrangement and method for making

A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

Semiconductor device having fins and method of fabricating the same

A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

Semiconductor device structure with inner spacer layer

The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.

Air inner spacers

A method includes forming a gate structure across a channel region from a top view, the gate structure comprising a work function metal and a gate dielectric layer wrapping around the work function metal, the gate dielectric layer having a U-shaped cross-sectional profile; performing a first plasma etching process, by using a chlorine-containing reactant, on the gate structure; performing a second plasma etching process, by using a bromine-containing, reactant on the gate structure.

Semiconductor device and method for manufacturing the same

A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.

Inner spacer formation in multi-gate transistors

The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

Pattern fidelity enhancement

In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gate electrode and the dielectric layer. A gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. A conductive contact overlies an individual source/drain region. A width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. The conductive contact extends along the curved sidewall of the gate capping layer.

Dielectric protection layer in middle-of-line interconnect structure manufacturing method

A method for fabricating a semiconductor device comprises forming a gate electrode structure over a first region of a semiconductor substrate, and forming a source/drain region on a second region of the semiconductor substrate. The gate electrode structure comprises a metal gate electrode layer, a gate dielectric layer, and gate sidewalls. The second region of the semiconductor substrate is on an opposing side of the metal gate electrode layer. The method for fabricating a semiconductor device further comprises forming an interlayer dielectric layer over the source/drain regions and the gate sidewall, and forming an oxide layer over the source/drain region and the gate sidewall without substantially forming the second oxide layer on the gate electrode layer.

Method of fabricating a semiconductor device

The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Spacer structure for semiconductor device and method for forming the same

The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Semiconductor device with reduced loading effect

Growing community of inventors

Hsin-Chu, Taiwan

Li-Te S Lin