Massachusetts Institute of Technology

Nanyang Technological University

National University of Singapore

Li-Shiuan Peh

Pilsoon Choi

Chirn-Chye Boon

Jurgen Michel

Li Hong Zhang

Eng Kian Kenneth Lee

Soo-Jin Chua

Siau Ben Chiah

Bing Wang

Wenjia Zhang

Zhaomin Zhu

Jason Hao Gao

Nadesh Ramanathan

Suhaib Fahmy

A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed. Also, a logic circuit comprising: a low voltage logic input; a high supply voltage input; a circuit ground voltage input; a high voltage output; a first tail device made from a first semiconductor material; and a second tail device made from a second different semiconductor material; wherein the first and second tail devices are coupled, in series, between the high voltage output and the circuit ground voltage input; and wherein respective gates of the first and second tail devices are coupled, in parallel, to the low voltage logic input.

High voltage logic circuit

A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

Method of forming an integrated circuit and related integrated circuit

A method () of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing () the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding () at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

An integrated circuit () adapted for mobile communication is disclosed. The circuit comprises a first device layer formed of a first semiconductor material and having at least a first circuit portion (); and a second device layer formed of a second semiconductor material different to the first semiconductor material and having at least a second circuit portion (), wherein the first and second device layers are integrally formed, and the first circuit portion is electrically coupled to the second circuit portion to enable the mobile communication using first and second wireless communication protocols. A related mobile computing device is also disclosed.

Integrated circuit adapted for mobile communication and related mobile computing device

Growing community of inventors

Cambridge, MA, United States of America

Li-Shiuan Peh