Taiwan Semiconductor Manufacturing Comp. Ltd.

Li-Shiuan Chen

Yung-Yao Lee

Li-Kong Turn

Chung-Hao Chang

Ping-Hsi Yang

Han-Ming Hsieh

Wei-Hong Chuang

One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.

Overlay sampling methodology

An iterative rinse for fabrication of semiconductor devices is described. The iterative rinse includes a plurality of rinse cycles, wherein each of the plurality of rinse cycles has a different resistivity. The plurality of rinse cycles may include a first rinse of a semiconductor substrate with de-ionized (DI) water and carbon dioxide (CO), followed by a second rinse the semiconductor substrate with DI water and CO. The first rinse has a first resistivity; the second rinse has a second resistivity lower than the first resistivity.

Iterative rinse for semiconductor fabrication

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Kaohsiung, Taiwan

Li-Shiuan Chen