Dinochip, Inc.

Alcatel Lucent

Other

Li-Sheng Chen

Sina Soltani

Radimir Shilshtut

Mudhafar Hassan-Ali

Francisco Moreno

Jeff Mendelson

Annie Rastello

Dziem Dinh Nguyen

Qian-Yu Tang

Huadong Shao

A technique to implement a network traffic management system with an integrated multidimensional floating point sorter is to store data such that it may be retrieved in a sorted fashion. Entries are stored into a memory according to time stamp value, represented in a floating point format, and the time stamp value is divided into at least two portions, exponent and mantissa. The memory is organized as a pointer memory. An integrated multidimensional floating point sorter may be implemented using integrated circuit technology using one or more integrated circuits. These integrated circuits may be used in management of network traffic, and provides quality of service (QoS) or class of service (CoS) control.

Managing network traffic using floating point format values

Network traffic is manages using a digital signal processing integrated circuit (DSP). The DSP performs one or more of the following functions on the incoming network traffic: classification, policing, congestion control, segmentation and reassembly, queuing, scheduling, shaping and label switching. The DSP may have one or a plurality of processing cores. In one embodiment of the invention, each processing core of the DSP is dedicated to specific traffic management layer. The DSP, used in management of network traffic, provides quality of service (QoS) or class of service (CoS) control.

Traffic management in digital signal processor

A Virtual Group Connection (VGC) scheme for grouping ATM connections. A plurality of VPCs, VCCs, or both are managed together as a single virtual data pipe having a pool of common connection resources (e.g., bandwidth, buffering, etc.) associated therewith. Shaping, grooming, policing, switching, and other traffic engineering operations may be performed on a VGC as a single connection hierarchy operable to be associated with a single customer.

Virtual group connection scheme for ATM architecture in an access node

Fractional or fuzzy time stamp values are used during processing network traffic. Handling fractional time stamp values permits scaling down of time stamp values, so that fewer bits, and memory, are needed to store each fractional time stamp value. According to a specific technique, departure times are set based on a quantity X plus Y/Z, where X is an integer, Y is a numerator, and Z is a denominator. The departure times are synchronized with the ideal departure times after (Z*X+Y) time units. A technique is provided to reduce cell delay variation.

Processing network packets using fractional time stamp values

A method and technique of managing network traffic using a digital signal processing integrated circuit (DSP). The DSP performs one or more of the following functions on the incoming network traffic: classification, policing, congestion control, segmentation and reassembly, queuing, scheduling, shaping and label switching. The DSP may have one or a plurality of processing cores. In one embodiment of the invention, each processing core of the DSP is dedicated to specific traffic management layer. The DSP, used in management of network traffic, provides quality of service (QoS) or class of service (CoS) control.

A technique to implement a network traffic management system with an integrated multidimensional floating point sorter () is to store data such that it may be retrieved in a sorted fashion. Entries are stored () into a memory according to time stamp value, represented in a floating point format, and the time stamp value is divided () into at least two portions, exponent and mantissa. The memory is organized as a pointer memory (, and). An integrated multidimensional floating point sorter may be implemented using integrated circuit technology using one or more integrated circuits (). These integrated circuits may be used in management of network traffic, and provides quality of service (QoS) or class of service (CoS) control.

Network traffic management system with floating point sorter

Network processing using fractional time stamp values

A scheme for implementing GFR service in an ATM environment, e.g., an access node's ATM switch fabric. Regulation of a GFR flow is throttled between two modes, a guaranteed rate mode and a non-guaranteed rate mode, depending upon timestamps computed by applicable traffic policer/shaper algorithms. A scheduler is operably coupled to a policing block for scheduling cells from a guaranteed flow queue for transport via the ATM fabric at a guaranteed rate upon determining the onset of a guaranteed service frame. The scheduler switches to non-guaranteed rate mode for scheduling cells from the flow queue at a non-guaranteed rate when a timestamp (TS) for transmission at the non-guaranteed rate is earlier than a timestamp (TS) for transmission of a next guaranteed service frame at the guaranteed rate.

System and method for implementing GFR service in an access node's ATM switch fabric

A hierarchical scheduler architecture for use with an access node terminal disposed in an access network portion. Ingress flows aggregated via a plurality of aggregation layers are switched through an ATM fabric that segregates flow cells based on service priority categories (planes). Thus, a two-dimensional scheduler employs arbitration on a per-aggregation layer, per-service priority basis, wherein each layer is responsible for selecting the most eligible flow from the constituent flows of that layer, which is forwarded to the next layer for arbitration. A service-based arbiter selects overall winner cells for emission through the fabric from winner cells generated for each service plane.

Hierarchical scheduler architecture for use with an access node

A multicast scheme for scheduling a root flow in an ATM environment. A buffer system including an index memory is operable to contain a plurality of leaf flow index values associated with the leaves and a root flow index associated with the root flow from the ingress interface. A pointer memory is provided wherein a plurality of circularly-linked pointers are indexed from the leaf and root flows. A cell memory is provided with a plurality of cell memory locations to which the linked pointers point. Root flow cells in the ATM environment are stored in the cell memory locations based on the root flow index. When a particular flow becomes eligible for scheduling, a copy of a root cell is obtained for emission, the root cell being located in a cell memory location that is pointed to by a linked pointer, to which the particular leaf flow is indexed.

Multicasting system and method for use in an access node's ATM switch fabric

A calendar heap structure and method for sorting N timestamp (TS) values in an ATM fabric scheduler implemented in an access network element. The heap structure is implemented using a radix value (R) for grouping the N TS values into a number of groups. Validity bits associated with the TS values are hierarchically arranged in a tree having log(N) levels, wherein the bottom layer's N bits correspond to pointers that point to linked lists of flows with respective TS values. Starting from the top level heap, each subsequent level's heaps are successively examined for determining which particular heap obtains a minimum value until a particular validity bit of the bottom level is reached, which validity bit points to the minimum TS.

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Petaluma, CA, United States of America

Li-Sheng Chen