Industrial Technology Research Institute

Li-Ren Huang

Ke-Horng Chen

Sy-Yen Kuo

Hong-Wei Huang

Cihun-Siyong Gong

Chi-Chun Hsu

Yung-Chang Chang

Chung-Wei Lin

Kai-Cheung Juang

Wei-Zen Chen

Chih-Jen Yang

Gin-Kou Ma

Huan-Ke Chiu

Chein-Wei Jen

Day-Uei Li

Chien-Fu Chang

Chun-Yen Wu

Po-Hsun Tu

Zen-Dar Hsu

Cheng-Hsun Lin

Yi-Feng Luo

Po-Sen Huang

Wen-Dar Hsieh

John-See Lee

Chun-Cheng Kuo

Chueh-hao Yu

Chia-Wrong Chang

Le-Shian Liu

Kung-Ming Ji

Chin-Ching Yeh

A processor capable of changing redundant processing node comprises a plurality of processing nodes and a plurality of comparators. The plurality of processing nodes comprises a first processing node, a second processing node, and a third processing node, wherein the first processing node performs a first computation, the second processing node selectively performs the first computation or a second computation, and the third processing node performs the second computation. The plurality of comparators comprises a first comparator and a second comparator, wherein the first comparator connects to the first and second processing nodes to compare whether the results of the first computation performed by the first and second processing nodes are identical, and the second comparator connects to the second and third processing nodes to compare whether results of the second computation performed by the second and third processing nodes are identical.

Redundant processing node changing method and processor capable of changing redundant processing node

A memory protection device is used for protecting a memory. The memory protection device includes a filtering unit and an encoding unit. The filtering unit searches an input data and outputs an encoding selection signal based on a bit component pattern of the input data. The encoding unit selects one or more encoding implementations among a plurality of encoding implementations based on the encoding selection signal from the filtering unit, to encode the input data.

Memory protection device and method

An embodiment of the invention provides a liquid-level sensor to detect liquid-level information of a liquid to be tested in a container. The sensor includes an electrode, a sensing circuit, an amplifier and a controller. The electrode is disposed on the outer surface of the container, comprising a first electrode and a second electrode. The sensing circuit is coupled to a first electrode and a second electrode, and receives a clock signal to generate a first voltage signal and a second voltage signal. The amplifier receives the first voltage signal and the second voltage signal to output an output voltage. The controller acquires liquid-level information of the liquid to be tested according to the output voltage and a voltage-volume table.

Apparatus for detecting liquid level

An impedance analysis device adapted to an object under test (OUT) includes a signal generator, a signal analysis unit and a processing unit. The signal generator outputs a pulse signal to the OUT. The signal analysis unit acquires a response signal which the OUT responds to the pulse signal, and analyzes the response signal to obtain an analysis parameter. The processing unit coupled to the signal analysis unit receives the analysis parameter, so as to obtain an impedance variation characteristic of the OUT.

Device and method for impedance analysis

A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit.

Chip with embedded non-volatile memory and testing method therefor

A two-piece wireless hearing improvement system having a pocket piece and an earpiece, wherein the pocket piece includes a microphone adapted to receive analog signals, a first processor coupled to the microphone to convert the analog signals to digital signals, and a first transceiver coupled to the processor to transmit the digital signals. The earpiece includes a second transceiver for receiving the digital signals, a second processor coupled to the second transceiver for converting the digital signals to analog signals, a speaker coupled to the second processor for transmitting the analog signals, and a movement detector for detecting relative movements between the earpiece and the pocket piece and generating a first signal according to the relative movements. The first processor provides signal compensation based on the first signal.

Wireless system and method thereof for hearing

A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a significant transition of an input signal. Each oscillator receives the detection signal and operates alternately in a clock and data recovery mode and a phase-locked mode. When the first oscillator operates in the clock and data recovery mode and outputs a first clock to control the flip-flop to output an output signal, the second oscillator operates in the phase-locked mode to adjust a frequency of a second clock. Before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.

Clock and data recovery circuits

A clock and data recovery apparatus and the method thereof are applied for burst mode clock and data recovery (CDR) in a passive optical network (PON). A phase-locked loop induces a first control signal and a first clock. A clock and data recovery circuit receives an incoming data having a first frequency and induces a second clock having one of second and third frequencies to sample the incoming data according to the second clock to obtain a recovered data, wherein the first frequency is between the second and third frequencies. Moreover, a controller induces a second control signal according to the incoming data (or the recovered data), the first clock, and the second clock to adjust the frequency of the second clock.

Clock and data recovery apparatus and method thereof

A power supply apparatus for supplying an output voltage to a load is provided, which comprises a power output unit, a feedback unit and a control unit. The power output unit adjusts and supplies the output voltage to the load in accordance with at least one driving signal. The feedback unit dynamically detects output condition of the power output unit and outputs the corresponding detection result. The control unit determines a skipping ratio for an internal clock in accordance with the detection result output from the feedback unit, and outputs the internal clock with a part of the pulses being skipped to act as the driving signal.

Power supply apparatus

A capacitor multiplier including a capacitor, a first voltage follower, a first impedance element, and a second impedance element is provided. The input terminal of the first voltage follower is electrically connected to the first terminal of the capacitor. Wherein, the voltage level of the output terminal of the first voltage follower changes along with the voltage level of the input terminal thereof. The first terminal of the first impedance element is electrically connected to the first terminal of the second impedance element. The second terminal of the first impedance element is electrically connected to the first terminal of the capacitor. The second terminal of the second impedance element is electrically connected to the output terminal of the first voltage follower.

Capacitor multiplier

A backlight device includes a light source module having a plurality of light sources, a detecting circuit, a control unit, and a pulse width modulation (PWM) driving circuit. The detecting circuit is used for detecting the brightness of the light source module and generating a detecting signal to the control unit, such that the control unit outputs a control signal according to the detecting signal. In addition, the PWM driving circuit is used for generating a PWM signal for driving the light source module. In the present invention, the PWM driving circuit adjusts the base frequency of the PWM signal according to the control signal without adjusting the duty cycle of the PWM signal, so as to control the brightness of the light sources.

Backlight device and method for controlling light source brightness thereof

A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELL(0&#x3c;x&#x2266;n). The delay cells DCELL&#x2dc;DCELLare connected in series to each other. Each of the delay cells DCELLis coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal t(0&#x3c;y&#x2266;n) of a delay cell DCELLamong the delay cells DCELL&#x2dc;DCELLused as output terminal of the delay line.

Delay line, analog-to-digital converting device and load-sensing circuit using the same

A DC-DC converter includes an error amplifier that includes an operational transconductance amplifier (OTA), a compensation circuit, and a fast transient controller. The OTA includes a compensation resistor, a compensation capacitor of C, and a Miller circuit. The equalization capacitance generated by the compensation capacitor and the Miller circuit is (1+k) C. The Miller circuit includes three transistors operated in the triode region. The ratio of the current through the transistors is 1:mk:(1&#x2212;m)k. The current through the compensation capacitor in a second mode is (1+mk) times that in a first mode. The fast transient controller switches the Miller circuit between the first and second modes according to a feedback voltage dependent on the output voltage of the DC-DC converter.

DC-DC converter and error amplifier thereof

A laser driver. The laser driver comprises a diode driver, a power detector, a first extreme detector, a second extreme detector and a current controller. The diode driver receives bias and modulation currents to control a laser diode for generating light signals. The power detector detects optical power of the light signals. The first and second extreme detectors, both coupled to the power detector, detect the first and second extreme values among detected optical power. The first extreme value is either the maximum or the minimum optical power of the light signals, while the second extreme value is the other.

Dual loop automatic power control for laser driver

A direct current (DC) offset canceling circuit of a trans-impedance amplifier and an automatic gain control trans-impedance amplifier is provided, including: a trans-impedance amplifier for receiving an input current and converting the input current into a first voltage signal, while the trans-impedance amplifier is provided with a plurality of inverters connected in series, wherein a sample node is defined between each inverter; a DC detector for retrieving and comparing the signals at any sample node, thereby generating a trigger signal according to the comparison; a DC eliminator for providing a path to the DC component of the input current in response to the triggering by the signal trigger, to eliminate the DC component; a reference voltage unit for outputting a reference voltage value; and a voltage output amplifier for comparing the reference voltage and the first voltage signal, to amplify the output of a second voltage signal.

Growing community of inventors

Taipei County, Taiwan

Li-Ren Huang