Qualcomm Incorporated

Li Qiu

Satish Raj

Rajesh Verma

Arun Tyagi

Mathew Philip

Shiva Ram Chandrasekaran

Satyanarayana Sahu

Thomas E Little

Xiang Matthew Song

Hsiu C Ma

Calvin V Ho

Hsiaohui Wu

Frederick C Jen

A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

Systems and methods to separate power domains in a processing device

A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel.

Method to automatically add power line in channel between macros

A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a method includes, after a layout phase of generating a design of a circuit, receiving timing information related to the design of the circuit. The method also includes selectively identifying at least one gate of a combinational logic portion of the design of the circuit to be modified to respond to a test enable signal, the at least one gate identified at least partially based on the timing information. The method also includes modifying the at least one gate. The at least one modified gate is fixed at a constant level during a test mode and is dynamically changeable during a functional mode of operation of the circuit.

System and method of test mode gate operation

A system and method of connecting a macro cell to a system power supply network is disclosed. In a particular embodiment, the method includes determining a distance of an edge of the macro cell from a power line or a ground line of the system power supply network. The method further includes selectively adding at least one line to the system power supply network.

System and method of connecting a macro cell to a system power supply

In a particular embodiment, a method is disclosed that includes detecting a first pitch between at least two lines (e.g. a power line and a ground line) of a first reference macro. The method also includes generating a virtual grid based on the first pitch and aligning at least a second macro to the virtual grid.

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Palo Alto, CA, United States of America

Li Qiu