Winbond Electronics Corporation

Li-Ming Wang

Kao-Tsair Tsai

Hsi-Chuan Chen

Jung-Ho Chang

Bor-Ru Sheu

Sen-Huan Huang

Wen-Kuei Hsieh

Hong-Hsiang Tsai

Haochieh Liu

Systems for determining width/space limits for product mask layouts. A mask writer generates a first pattern on a test mask corresponding to a test mask layout. A lithography tool generates a second pattern on a wafer corresponding to a first pattern on a test mask by a lithography process using a preset exposure dose. A metrology tool measures widths of the first and second pattern. A controller determines a width/space limit for the product mask layout according to the width difference between the first and second pattern.

Systems and methods for determining width/space limits for a mask layout

Systems and methods for determining width/space limits for mask layout

A method of correcting a mask pattern is provided. First, an original writer drawing data of a circuit layout pattern is inputted. Then, according to the original writer drawing data, a correcting writer rule is selected by searching from a look-up table. According to the correcting writer rule, the original writer drawing data is corrected to obtain a corrected writer drawing data of the circuit layout pattern.

Method of correcting mask pattern

A photomask set and a photolithographic operation suitable for forming a desired pattern on a photoresist layer. The photomask set includes a plurality of photomasks each having a different pattern thereon. To form an overall pattern on the photoresist layer, each photomask is used in turn in a multi-exposure operation.

Photomask set for photolithographic operation

A multilayer photoresist process in photolithography, which is applicable on a substrate having a composite photoresist layer with a desired thickness formed thereon. The present invention provides a process, comprising the following steps. A photoresist layer is formed on a substrate, and subsequently exposed through a photomask, followed by the developing process to pattern the photoresist. Then, the patterned photoresist layer is stabilized. This sequence is repeated untill at least another one layer is deposited and patterned on the substrate. Each photoresist layer has almost the same pattern with the underlying patterned photoresist layer. Many thin photoresist layers are accumulated to form a composite photoresist layer with a desired thickness.

Multilayer photoresist process in photolithography

A method for suppressing the optical proximity effect bias within a wafer by compensating the optical proximity effect within the wafer includes the steps of: Firstly, performing a first exposure step with a first exposure parameter setup to transfer a pattern from a photomask to a first die of the wafer. Secondly, performing a second exposure step with a second exposure parameter setup to transfer the pattern from the photomask to a second die of the wafer, wherein the first and second exposure parameter setups are adjusted according to the local optical proximity effect bias of the dies within the wafer. The exposure parameter setup can be numerical aperture setup, partial coherence setup, exposure energy setup, exposure time setup, exposure light intensity setup, or best focus setup. The light source used in the exposure steps can be an I-line, G-line, KrF laser, ArF laser, X-ray, or e-beam.

Method for suppressing optical proximity effect bias within a wafer

A method for the mitigation of the generation of side-lobes in a photolithography process is described. The method includes the steps of forming a photoresist layer on a semiconductor substrate. An exposure process is conducted on the photoresist layer with a phase-shifting mask, transferring the pattern of the mask on the photoresist layer. After this, a post-exposure baking process is conducted on the photoresist layer after it has been exposed, followed by performing a development process to complete the patterning of the photoresist layer.

Method for preventing side-lobes in photolithography

A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug.

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Taoyuan, Taiwan

Li-Ming Wang