Taiwan Semiconductor Manufacturing Comp. Ltd.

Illumina Corporation

Li-Min Hung

Jung-Huei Peng

Shang-Ying Tsai

Yao-Te Huang

Chin-Yi Cho

Chia-Hua Chu

Chun-Wen Cheng

Yi-Chuan Teng

Hsin-Ting Huang

Hui Han

Danny Yuan Chan

Shane Bowen

Yu-Chia Liu

Yi-Chien Wu

Sang Ryul Park

Nien-Tsung Tsai

Sang Park

A flow cell includes: a first substrate; a second substrate; a first resin layer disposed over an inner surface of the first substrate; a second resin layer disposed over an inner surface of the second substrate; a first plurality of biological capture sites located at the first resin layer; a second plurality of biological capture sites located at the second resin layer; and a polymer layer interposed between the first resin layer and the second resin layer, such that the first substrate is attached to the second substrate via at least the first resin layer, the polymer layer, and the second resin layer, wherein the polymer layer defines a plurality of microfluidic channels that extend through polymer layer.

Method to produce chemical pattern in micro-fluidic structure

The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.

Structure for integrated microphone

An embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.

Method for manufacturing a microphone

The present disclosure provides flow cells and methods of fabricating flow cells. The method includes combining three portions: a first substrate, a second substrate, and microfluidic channels between the first substrate and the second substrate having walls of a photoresist dry film. Through-holes for inlet and outlet are formed in the first substrate or the second substrate. Patterned capture sites are stamped on the first substrate and the second substrate by a nanoimprint lithography process. In other embodiments, parts of the patterned capture sites are selectively attached to a surface chemistry pattern formed of silicon oxide islands each disposed on an outcrop of a soft bottom layer.

Some embodiments of the present disclosure provide a microelectromechanical systems (MEMS). The MEMS includes a semiconductive block. The semiconductive block includes a protruding structure. The protruding structure includes a bottom surface. The semiconductive block includes a sensing structure. A semiconductive substrate includes a conductive region. The conductive region includes a first surface under the sensing structure. The first surface is substantially coplanar with the bottom surface. A dielectric region includes a second surface not disposed over the first surface.

Micro-electro-mechanical system and manufacturing method thereof

A wafer seal ring may be formed on a wafer having a pattern structure with a pattern density. The wafer seal ring pattern structure may include a plurality of lines having a width and a spacing that may be approximately equal to a width and a spacing of die bond rings on the wafer. The wafer having the wafer seal ring formed thereon may be bonded to a wafer that may not have a wafer seal ring. A pair of wafers may be formed with respective wafer seal rings formed in a corresponding manner. The pair of wafers may be bonded together with the wafer seal rings aligned and bonded together to form a seal ring structure between the bonded wafers.

Method and apparatus for a wafer seal ring

A semiconductor device includes a substrate, an interconnection layer, an outgassing layer, and a patterned outgassing barrier layer. The interconnection layer is over the substrate. The outgassing layer is over the interconnection layer. The patterned outgassing barrier layer is over the outgassing layer. The patterned outgassing barrier layer includes a plurality of barrier structures and a plurality of openings. The plurality of openings expose a portion of an upmost surface of the outgassing layer, and a bottommost surface of the patterned outgassing barrier layer is substantially coplanar with the upmost surface of the outgassing layer.

Semiconductor device and package and manufacturing method thereof

According to an exemplary embodiment of the disclosure, a method of removing a waste part of a substrate is provided. The method includes: using a laser to partially drill the substrate to define the waste part; and applying megasonic vibration to the substrate to remove the waste part from the substrate.

Method of removing waste of substrate and waste removing device thereof

In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.

Wafer level packaging techniques

The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate; a silicon oxide layer formed on one side of the first silicon substrate; a second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates; and a diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates, wherein the first plate and the diaphragm are configured to form a capacitive microphone.

Structure and method for integrated microphone

A structure comprises a first semiconductor substrate, a first bonding layer deposited on a bonding side the first semiconductor substrate, a second semiconductor substrate stacked on top of the first semiconductor substrate and a second bonding layer deposited on a bonding side of the second semiconductor substrate, wherein the first bonding layer is of a horizontal length greater than a horizontal length of the second semiconductor substrate, and wherein there is a gap between an edge of the second bonding layer and a corresponding edge of the second semiconductor substrate.

Growing community of inventors

Longtan, Taiwan

Li-Min Hung