Qualcomm Incorporated

Nuvolta Technologies (Hefei) Co., Ltd.

Li Lu

Dinesh Jagannath Alladi

Mohammad Meysam Zargham

Yan Wang

Chinmaya Mishra

Liang Dai

Masoud Roham

Arul Balasubramaniyan

Omid Rajaee

Meysam Azin

Kentaro Yamamoto

Damin Cao

David Ta-hsiang Lin

Changsok Han

Paul Gunaratnam

Olivier Gerard Metayer

Anees Habib

Shuang Zhu

An apparatus includes a first sampling switch coupled between a first voltage bus and a sampling capacitor, a first clock generator configured to produce a first gate drive signal fed into a gate of the first sampling switch, the first clock generator comprising a first capacitive coupled clock shifter, a first reset circuit and a second reset circuit, a second sampling switch coupled between a second voltage bus and the sampling capacitor, and a second clock generator configured to produce a second gate drive signal fed into a gate of the second sampling switch, the second clock generator comprising a second capacitive coupled clock shifter, a third reset circuit and a fourth reset circuit.

Voltage sampling apparatus and method

Aspects of the disclosure relate to an apparatus for wireless communication. The apparatus may include a set of power detectors configured to generate a set of analog signals related to a set of output signal power levels of a set of transmit chains of a transmitter, respectively; an analog summer; a set of switching devices configured to send a selected one or more of the set of analog signals to the analog summer, and substantially isolated unselected one or more of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more of the set of analog signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal; and a controller configured to control the set of switching devices.

Transmitter output signal power measurement apparatus

Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.

Successive approximation register analog-to-digital converter chopping

Certain aspects of the present disclosure provide apparatus and techniques for analog-to-digital conversion using a time-to-digital converter (TDC). For example, certain aspects provide a quantizer using a TDC. The quantizer may include at least one first capacitive element and a set of switches configured to selectively couple a first terminal and a second terminal of the at least one first capacitive element to at least one input voltage source. The TDC may also include a reference voltage source, at least one switch coupled between the second terminal of the at least one first capacitive element and an output of the reference voltage source, a current source selectively coupled to the first terminal of the at least one first capacitive element, and a voltage sense circuit coupled to the first terminal of the at least one first capacitive element.

Time-to-digital converter (TDC)-based quantizer

A device and method for analog to digital conversion is disclosed. The device can have a first amplifier operable to receive an input voltage and output a first control signal. The device can also have a first voltage-controlled oscillator (VCO) operably coupled to the first amplifier and configured to output a first signal based on the first control signal, the first signal having a sensor frequency. The device can also have a first switched-capacitor resistor operably coupled to the first VCO and to the first amplifier, the first switched-capacitor resistor configured to receive and be controlled by the sensor frequency. The device can also have a sensor counter operably coupled to the first VCO and configured produce a sensor count based on the sensor frequency. The device can also have a register configured provide a digital output proportional to the input voltage based on the sensor count.

Closed loop linearized VCO-based ADC

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San Diego, CA, United States of America

Li Lu