Cadence Design Systems, Inc.

Li-Ling Ma

Roland Ruehl

Mathew Koshy

Tianhao Zhang

Eitan Cadouri

Xiaojun Wang

Min Cao

Udayan Anand Gumaste

Haifang Liao

Krzysztof Antoni Kozminski

Xinming Tu

Xu Zhu

Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Method and system for parallel processing of IC design layouts

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San Jose, CA, United States of America

Li-Ling Ma