Mediatek Corporation

Mediatek Incorporation

Li-Lien Lin

Wen-Yi Wu

Jia-Horng Shieh

Ching-Wen Hsueh

Jyh-Shin Pan

Chao-Yi Wu

Chien-Chung Wu

Hong-Ching Chen

Pi-Hai Liu

Chih-Ching Yu

Li-Chun Tu

Shih-Hsin Chen

Meng-Hsueh Lin

Shih-Ta Hung

Wei-Hung Huang

You-Wen Chang

Chien-Hsun Tung

Jui-Tse Lin

Ta Hsing Liu

Ching-Hao Yu

An output queue of a multi-plane network device includes a first processing circuit, a plurality of storage devices and a second processing circuit. The first processing circuit generates packet selection information based on an arrival sequence of a plurality of packets. The storage devices store a plurality of packet linked lists for the output queue. The second processing circuit dequeues a packet from the output queue by selecting a linked list entry from the packet linked lists according to the packet selection information.

Output queue of multi-plane network device and related method of managing output queue having multiple packet linked lists

An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.

Error correction method and error correction apparatus utilizing the method

A multi-channel memory apparatus is provided. The multi-channel memory apparatus includes a host interface, storage channels, an error correcting module, and a multiple memory access module. The host interface is arranged to receive and transmit data from and to a host device. Each storage channel is coupled to a memory device for storing the data. The error correcting module is shared by the storage channels, includes an error correction code engine and a data buffer, and is arranged to perform error correction code encoding on the data to be stored into the memory devices and perform error correction code decoding on the data read out from the memory devices. The multiple memory access module is coupled between the storage channels and the error correcting module and arranged to perform multiple access control of the storage channels for the error correcting module.

Multi-channel memory apparatus and method thereof

One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit.

Storage controller with encoding/decoding circuit programmable to support different ECC requirements and related method thereof

An error correction device is provided. When an error of an incorrect data group stored in a memory is detected, a memory controller of the error correction device executes a burst read, burst write or burst read-modify-write (RMW) operations to the memory instead of the conventional single read-modify-write (RMW) operation, thereby reducing the occupied bandwidth of the memory.

Error correction devices and correction methods

A method for decoding multiword information comprises steps (a) to (e). In step (a), a multiword information cluster, e.g., ECC, including high protective codewords, e.g., BIS, and low protective codewords, e.g., LDC, is provided. In step (b), the high and low protective codewords are stored into a first memory, e.g., DRAM. In step (c), the high protective codewords are decoded to generate high protective word erasure indicators showing whether decoding errors occur. In step (d), the high protective word erasure indicators are stored into a second memory, e.g., SRAM. In step (e), the low protective codewords are decoded. In the meanwhile, an erasure bit for a low protective codeword is marked by finding high protective codewords close to the low protective codeword in the multiword information cluster and looking up the high protective word erasure indicators of the high protective codewords close to the low protective codeword.

Method for decoding multiword information

A reproduction data recording method for an optical storage medium. The method comprises storing additional data to a first temporary region of a memory device; reading the first recorded data from the optical storage medium and storing the first recorded data to the first temporary region; reading a data segment of the second recorded data from the optical storage medium and storing the data segment to a second temporary region of the memory device; reading the first recorded data from the first temporary region and the data segment from the second temporary region, and decoding the first recorded data and the data segment to confirm accuracy of the first recorded data; reading the first recorded data and the additional data from the first temporary region, and encoding the first recorded data and the additional data to generate encoded data; and writing the encoded data to the optical storage medium.

Reproduction data recording methods

An apparatus for accessing and transferring optical data has a memory supporting the page-mode function, an accessing device used to access an error correction block from the optical storage medium and store it into the memory to make the portion of data in the same column of the error correction block stored in a particular locality greater than the portion of data in the same row of the error correction block stored in the particular locality, and an error correction decoder used to access the data of the error correction block to perform the error correction process. The apparatus uses the feature of the DRAM, such as page-mode function, and the data arrangement of the memory to improve the access efficiency of the memory. The apparatus can thus increase the access speed of the error correction decoder and improve the accessing efficiency.

Apparatus for accessing and transferring optical data

An error correction device is provided. When an error of a data group stored in a dynamic random access memory (DRAM) device is detected, a memory controller of the error correction device executes a burst read and write, burst write or burst read-modify-write (RMW) operations to the DRAM instead of the conventional single read-modify-write (RMW) operation, thereby reducing the occupied bandwidth of the DRAM.

An integrated apparatus for multi-standard optical media includes a compact disc/digital versatile disc (CD/DVD) processor, a high-definition DVD (HDDVD) processor and a Blu-ray disc (BD) processor; a memory unit connected to the CD/DVD processor, the HDDVD processor and the BD processor to provide a storage resource; and a shared error correction code (ECC) engine for encoding or decoding the CD/DVD data stream, the HDDVD data stream and the BD data stream. Therein, the ECC engine further has a syndrome/parity generator to encode the data stream or to obtain the syndrome information from the data stream; and an erasure generator to obtain the possible error position information from the data stream. Thereby, the complexity and cost of the integrated apparatus can be reduced.

Integrated apparatus for multi-standard optical storage media

An embedded system for programming a programmable device including a micro controller and an I/O interface. The programmable device includes a pin set for signal delivery. The micro controller device controls the programmable device via the pin set. The I/O interface receives a program code provided externally. The micro controller executes a command sequence to program the program code into the programmable device via the pin set, and the programmable device uses the program code to provide the specific function. The command sequence may also be provided externally and sent to the micro controller via the well-known general I/O interface.

Embedded system

Methods and apparatus for extracting a portion of data from a plurality of BIS data are disclosed. The portion of data can be extracted from the plurality of BIS data stored in a first storage unit when those BIS data are accessed by other components. Alternatively, the extraction of the portion of data can be performed when the plurality of BIS data is written into the first storage unit. The extracted data are stored in a second storage unit to improve the accessing efficiency thereof.

Method and apparatus for extracting specific data from BIS data

An accessing/transferring apparatus has a first memory having multiple memory banks, each of the memory banks having multiple logical memory sections, each of the logical memory sections forming a memory matrix; a memory controller that uses the page-mode function or alternate-bank-access function of the first memory to write the data of the error correction block into the logical memory sections along a column direction; and an error correction decoder using the page-mode function or alternate-bank-access function of the first memory to access the data of the error correction block from the logical memory sections along the row direction. The present invention uses the features of a dynamic random access memory (DRAM), such as page-mode function and alternate-bank-access function, and the data arrangement of the memory to improve the access speed of the memory to increase the accessing efficiency of optical data.

The present invention is a method and system for encoding digital data. The encoding system proceeds the step of calculating error detection code and the step of scrambling the main data at the same time to decrease times for the access to the first memory. The present invention comprises a second memory. The encoding system can access more than one recording column per-time, which further decreases times for the access to the first memory.

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Hsinchu, Taiwan

Li-Lien Lin