Zhuhai Chuangfeixin Technology Co., Ltd.

Leland Stanford Junior University

Maxim Integrated Products, Inc.

Thin Film Electronics Asa

Gallop Creation USA Inc.

Li Li

Zhigang Wang

Minnie M Sarwal

Purvesh Khatri

Atul J Butte

Tara Sigdel

Amit Kaushal

Wenzhong Xiao

Klaus Kunze

Arvind Kamath

Wenzhuo Guo

Samuel Strober

Aditi Chandra

Junfeng Mei

Mao Takashima

Amit Subhash Kelkar

Inna Tregub

Xuejun Ying

Brian Bedwell

Xu Huang

Yongqiang Zheng

Jun Li

Brian S Poarch

Aspects of the present invention include methods for determining a transplant category of a subject having a transplant. Common mechanisms of rejection injury are uncovered across different tissue transplants, and provide a means to understand rational drug design. Various sources of tissues are examined form the patient for understanding AR mechanism (graft biopsy), as well as monitoring by minimal invasive means (blood) or non-invasive means (urine for the kidney allograft). For biomarker discovery different categories of markers are examined such as genes, proteins, peptides and antibodies. These biomarkers can help determine the subject's transplant category (e.g., acute allograft rejection (AR), stable allograft (STA), BK viremia, BK nephritis, drug toxicity or chronic allograft injury (CAI), and the like). Also provided are compositions, systems, kits and computer program products that find use in practicing the subject methods. The methods and compositions find use in a variety of applications.

Protein and gene biomarkers for rejection of organ transplants

An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate.

Antifuse OTP structures with hybrid low-voltage devices

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor, and an antifuse capacitor. The select transistor includes a first high-voltage junction formed in the substrate and a first low-voltage junction formed in the substrate. The antifuse capacitor includes a second high-voltage junction formed in the substrate and a second low-voltage junction formed in the substrate.

Antifuse OTP structure with hybrid junctions

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first low-voltage junction formed in the substrate, and a second low-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first low-voltage junction and the second low-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third low-voltage junction formed in the substrate, and a fourth low-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third low-voltage junction and the fourth low-voltage junction.

Antifuse OTP structure with hybrid device and hybrid junction for select transistor

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first high-voltage junction formed in the substrate, and a second high-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first high-voltage junction and the second high-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third high-voltage junction formed in the substrate, and a fourth high-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third high-voltage junction and the fourth high-voltage junction.

Antifuse OTP structures with hybrid devices and hybrid junctions

A humidity detecting device includes a substrate, a humidity sensor mounted on the substrate, a vent mounted to the humidity sensor, wherein the vent is configured to guide moisture and air from interior of a sample to the humidity sensor, and a spike fixedly coupled to the humidity sensor. The spike can penetrate and hook to the sample, which attaches the humidity sensor to the sample.

Humidity detection device for smart diaper

Methods are provided for determining whether a subject has a graft tolerant phenotype. In practicing the subject methods, the expression level of one or more gene in a sample from the subject, e.g., a blood sample, is assayed to obtain a gene expression result, where the gene expression result includes a result for a biomarker of graft tolerance. The obtained gene expression result is then employed to determine whether the subject has a graft tolerant phenotype. Also provided are compositions, systems and kits that find use in practicing the subject methods. The methods and compositions find use in a variety of applications, including the determination of an immunosuppressive therapy regimen.

Biomarkers for determining an allograft tolerant phenotype

An antifuse structure includes a first electrode layer, an inter-metal dielectric layer over the first electrode layer, and a via in the inter-metal dielectric layer. The via penetrates through the inter-metal dielectric layer exposing a portion of the first electrode layer. An antifuse layer is deposited in the via and over the portion of the first electrode layer. A second electrode is disposed in the via and over the antifuse layer. An interconnect layer may be deposited over the inter-metal dielectric layer and in electrical contact with the second electrode in the via.

Antifuse structure in via hole in interplayer dielectric

Methods are provided for determining whether a subject has a graft tolerant phenotype. In practicing the subject methods, the expression of at least 5 genes in a sample from the subject, e.g., a blood sample, is assayed to obtain a gene expression result for the at least 5 genes. The obtained gene expression result for the at least 5 genes is then employed to determine whether the subject has a graft tolerant phenotype. Also provided are compositions, systems and kits that find use in practicing the subject methods. The methods and compositions find use in a variety of applications, including the determination of an immunosuppressive therapy regimen.

Methods and compositions for determining a graft tolerant phenotype in a subject

Printable dopant formulations, methods of making such dopant formulations, and methods of using such dopant formulations are disclosed. The dopant formulations provide a printable dopant ink with a viscosity sufficient to prevent ink spreading when deposited in a pattern on a substrate. Furthermore, an ion exchange purification process provides the dopant formulation with a reduced metal ion concentration, and thus a relatively high purity level. Consequently, the dopant residue remaining on the substrate after curing and/or dopant activation process is relatively uniform, and therefore can be easily removed.

Dopant inks, methods of making dopant inks, and methods of using dopant inks

A device includes sidewalls formed in a wafer surface, where the sidewalls descend to a recessed surface. The recessed surface generally promotes resist coverage on the wafer surface, including corners (e.g., junctions between the wafer surface and various surface topographies, such as cavities, the recessed surface, and so forth) on the wafer. In one or more implementations, a wet etching procedure is used to form the sidewalls and recessed surface. A resist material (e.g., a photoresist material) is deposited onto the wafer surface, where the photoresist fully covers one or more of the top corners of the wafer surface. In one or more implementations, the recessed surface is positioned adjacent a trench formed in the wafer to promote resist coverage on the top surface of the wafer.

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Fremont, CA, United States of America

Li Li