Taiwan Semiconductor Manufacturing Comp. Ltd.

Li-Kong Turn

Fei-Gwo Tsai

Jui-Ping Chuang

Chung-Hao Chang

Ming-Shane Lu

Yi-Rem Chen

Chi-Hung Liao

Chun-Hung Lin

Hsueh-Yi Chung

Dong-Hsu Cheng

Wei-Yu Su

Han-Ming Sheng

Chih-Jen Yu

Keh-Wen Chang

Yi-Chang Sung

Juin-Hung Lin

Louie Liu

Ming-Huei Tseng

Ching-Yu Chang

Hung-Jui Kuo

Chin-Hsiang Lin

Dian-Hau Chen

Hua-Tai Lin

Yung-Yao Lee

Kuei Shun Chen

Yi-Ming Dai

Heng-Jen Lee

Chia-Hsiang Chen

Ko-Bin Kao

Bang-Chein Ho

Tsung-Chih Chien

Chun-Hao Chang

Chih-Chien Hung

Feng-Liang Lai

Shang-Yun Huang

Li-Wei Kung

Che-Rong Laing

Chun-Sheng Wang

Hsiang-Chung Liu

Li-Shiuan Chen

Ping-Hsi Yang

Hsin-Chun Chiang

Chien-Hsing Wu

Ham-Ming Hsieh

Cheng-Cheng Guo

De-Ming Liang

Chun-Mei Lee

Han-Ming Hsieh

A developing method is provided. The developing method includes rotating a wafer. The developing method also includes dispensing, through a first nozzle, a developer solution onto the rotated wafer through a first nozzle at a first rotating speed. The developing method further includes dispensing, through a second nozzle, a rinse solution onto the rotated wafer through a second nozzle at a second rotating speed. The second rotating speed is less than the first rotating speed. In addition, the developing method includes simultaneously moving the first nozzle and the second nozzle during either the dispensing of the developer solution or the dispensing of the rinse solution.

Developing method

A developing method comprises steps as follows. A wafer is rotated. A developer solution is dispensed onto the rotated wafer through a first nozzle. The first nozzle is moved back and forth between a first position and a second position, in which moving the first nozzle back and forth is performed such that the first nozzle moving forward to the second position is reversed at the second position and that the first nozzle moving forward to the first position is reversed at the first position, and the first position and the second position are directly over the wafer, and the developer solution is dispensed through the first nozzle when moving the first nozzle back and forth between the first position and the second position.

A developing method includes rotating a wafer. A developer solution is dispensed onto the rotated wafer through a first nozzle. The first nozzle is moved from a first position to a second position. The first position and the second position are over the wafer and within a perimeter of the wafer when viewed from a top of the wafer. The developer solution is dispensed through the first nozzle when moving the first nozzle from the first position to the second position. The first nozzle is moved back from the second position to the first position immediately after the first nozzle is moved from the first position to the second position. The developer solution is dispensed through the first nozzle when moving the first nozzle from the second position to the first position.

Systems and methods are provided for edge bead removal. A laser beam of approximately a wavelength is received. The laser beam is delivered along a predetermined beam path. The laser beam is projected on an edge portion of a wafer for edge bead removal.

Systems and methods for edge bead removal

A tool and a method of developing are provided. In various embodiments, the method of developing includes rotating a wafer at a first rotating speed. The method further includes dispensing a developer solution onto the wafer at the first rotating speed by a first nozzle above the wafer, wherein the first nozzle moves back and forth along a path during dispensing the developer solution. The method further includes rotating the wafer at a second rotating speed to spread the developer solution onto the wafer uniformly. The method further includes dispensing a rinse solution onto the wafer at the second rotating speed by a second nozzle above the wafer.

Tool and method of developing

One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.

Overlay sampling methodology

Methods for detecting and monitoring defects in a resist material are disclosed. In an example, a method includes forming a resist layer over a substrate; developing the resist layer; washing the developed resist layer with a thinner wash solution, wherein the washing reveals any negatively charged defects in the developed resist layer; and after the washing, inspecting for the negatively charged defects.

Defect monitoring for resist layer

Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.

Method and system for feed-forward advanced process control

A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer.

A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.

Method of inhibiting photoresist pattern collapse

A method for inspecting a phase shift photomask employs a phase shift photomask having an active pattern region. An optical property of the phase shift photomask is measured within the active pattern region, rather than, for example, a non-active pattern border region. By making the measurement within the active pattern region, performance of the phase shift mask may be properly assured. The method is particularly useful for inspecting attenuated phase shift photomasks to assure absence of side-lobes when photoexposing blanket photoresist layers.

Phase shift photomask performance assurance method

A static resistant reticle comprises a substrate and a patterning layer and is covered by an antistatic conductive film of quaternary amine (RN)Cl. A pellicle structure comprising an optically transparent membrane tightly stretched on a frame is also coated by an antistatic electro conductive film of a similar material. The reticle with the pellicle form a shielded structure isolating the reticle from ESD.

Reticle with antistatic coating

A method and system for identifying a defocus wafer by mapping a topography of each wafer in a first wafer batch using a level sensor apparatus (); calculating a focus spot deviation () from the data, the focus spot deviation () corresponding to a height by which a focus spot of a photo exposure module would be defocused by the topography; converting the focus spot deviation () to a corresponding wafer stage set point to which the photo exposure module is set, to focus the focus spot on each wafer in the wafer batch; and identifying a defocus wafer in the wafer batch, as a wafer having a topography that would defocus the focus spot, even when the photo exposure module is set to the wafer stage set point.

Method to predict and identify defocus wafers

An improved method of wafer height mapping using a wafer level sensor eliminates or substantially minimizes the 'spacing' in the wafer height mapping data usually caused by having an exposure field on a wafer whose width is less than the width of the measurement spot array of the wafer level sensor and also not being a multiple of the width of a single measurement spot. According to the improved method, the measurement spot array is first translated towards one edge of the exposure field and scanned. Then the measurement spot array is translated towards the other edge of the exposure field and scanned second time to map the area that was missed during the first mapping scan.

Method of wafer height mapping

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Taichung, Taiwan

Li-Kong Turn