Cadence Design Systems, Inc.

Kla-tencor Technologies Corporation

Li J Song

Kurt H Weiner

Taber H Smith

Akella V S Satya

Robert Thomas Long

Zhan-Zhong Yao

Nickhil Jakatdar

Srini Doddi

Rachid Salik

Narain D Arora

Hao Ji

Aki Fujimura

Raman K Nurani

Emmanuel Drego

Akella Vs Satya

Hao Jl

Vladimir D Federov

Akella V Satya

A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes.

Method and system performing RC extraction

A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.

Method and system performing block-level RC extraction

Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design.

Methods, systems, and computer program products for implementing compact manufacturing models in electronic design automation

The present invention relates to techniques for measuring integrated circuit interconnect process parameters. The techniques are applicable to any non-ideally shaped interconnects made from any type of conductive materials. Test structures are fabricated within an integrated circuit. Non-destructive electrical measurements are taken from the test structures to determine coupling capacitances associated with the test structures. A field solver uses the initial process parameters to determine design coupling capacitances. An optimizer then uses the measured coupling capacitances and the design coupling capacitances to determine the interconnect process parameters.

Measurement of integrated circuit interconnect process parameters

Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method of determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function. In specific implementations, the defect type is a short type defect or an open type defect. In a preferred implementation, the features may have any suitable polygonal shape, as is typical in a design layout.

Apparatus and methods for determining critical area of semiconductor design data

Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method for determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function. In specific implementations, the defect type is a short type defect or an open type defect. In a preferred implementation, the features may have any suitable polygonal shape, as is typical in a design layout.

Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.

Apparatus and methods for managing reliability of semiconductor devices

Disclosed are methods and apparatus for efficiently managing IC chip yield learning. In general terms, as each wafer lot moves through fabrication, yield information is obtained from each set of test structures for a particular process or defect mechanism. The nature of the yield information is such that it may be used directly or indirectly to predict product wafer test yield. In one implementation, the yield information includes a systematic yield (Y ), a defect density (DD), and a defect clustering factor (&agr;) determined based on the inspected test structure's yield. A running average of the yield information for each process or defect mechanism is maintained as each wafer lot is processed. As a particular wafer lot moves through the various processes, a product wafer-sort test yield may be predicted at any stage in the fabrication process based on the running-average yield information maintained for previously fabricated wafer lots.

Growing community of inventors

Fremont, CA, United States of America

Li J Song