Shenzhen Epostar Electronics Limited Co.

Li-Hsun Liu

Yu-Hua Hsiao

Chin-Yen Ko

A memory management method is provided. The method includes selecting a target physical programming unit; using a first read voltage corresponding to a first type physical page of the target physical programming unit to read a plurality of target memory cells of the target physical programming unit, so as to calculate a first bit value ratio; if the first bit value ratio is not smaller than a first preset threshold, using a second read voltage corresponding to the first type physical page of the target physical programming unit to read the plurality of target memory cells of the target physical programming unit, so as to calculate a second bit value ratio; and determining whether the first type physical page of the target physical programming unit is empty by comparing the first bit value ratio and the second bit value ratio.

Memory management method and storage controller

A memory management method is provided. The method includes performing a read retry operation to a target block stripe, and identifying a read retry recording table of the target block stripe; selecting a target read retry index value from one or more first read retry index values according to the one or more first read retry index values in the read retry recording table; using a target read retry option corresponding to the read retry index value to perform a read operation to the target block stripe; in response to determining that the read operation is successful, determining that the read retry operation is completed, and updating the read retry recording table according to the target read retry index value; and determining whether to perform a wear leveling operation to the target block stripe according to the latest read retry recording table.

A decoding method is provided. The method includes selecting a target word line among a plurality of word lines; respectively reading a plurality of target memory cells of the target word-line by using different X read voltage sets to obtain corresponding X Gray code summation sets; calculating a Gray code count summation difference of the Gray code count summations at the same sequence position respectively in N&#x2212;1 Gray code count summations between every pair of adjacent Gray code summation sets of the X Gray code summation sets, so as to obtain X&#x2212;1 Gray code count summation difference sets corresponding to all pairs of the Gray code summation sets; and deciding N&#x2212;1 optimized read voltages from X*(N&#x2212;1) read voltages belonging to the X read voltage sets according to the X&#x2212;1 Gray code count summation difference sets.

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Taoyuan, Taiwan

Li-Hsun Liu